/dts-v1/;

/ {
	compatible = "rockchip,rk3588s-evb4-lp4x-v10\0rockchip,rk3588";
	interrupt-parent = <0x01>;
	#address-cells = <0x02>;
	#size-cells = <0x02>;
	model = "RK3588S CoolPi 4B Board";

	aliases {
		csi2dcphy0 = "/csi2-dcphy0";
		csi2dcphy1 = "/csi2-dcphy1";
		csi2dphy0 = "/csi2-dphy0";
		csi2dphy1 = "/csi2-dphy1";
		csi2dphy2 = "/csi2-dphy2";
		dsi0 = "/dsi@fde20000";
		dsi1 = "/dsi@fde30000";
		ethernet1 = "/ethernet@fe1c0000";
		gpio0 = "/pinctrl/gpio@fd8a0000";
		gpio1 = "/pinctrl/gpio@fec20000";
		gpio2 = "/pinctrl/gpio@fec30000";
		gpio3 = "/pinctrl/gpio@fec40000";
		gpio4 = "/pinctrl/gpio@fec50000";
		i2c0 = "/i2c@fd880000";
		i2c1 = "/i2c@fea90000";
		i2c2 = "/i2c@feaa0000";
		i2c3 = "/i2c@feab0000";
		i2c4 = "/i2c@feac0000";
		i2c5 = "/i2c@fead0000";
		i2c6 = "/i2c@fec80000";
		i2c7 = "/i2c@fec90000";
		i2c8 = "/i2c@feca0000";
		rkcif_mipi_lvds0 = "/rkcif-mipi-lvds";
		rkcif_mipi_lvds1 = "/rkcif-mipi-lvds1";
		rkcif_mipi_lvds2 = "/rkcif-mipi-lvds2";
		rkcif_mipi_lvds3 = "/rkcif-mipi-lvds3";
		rkvenc0 = "/rkvenc-core@fdbd0000";
		rkvenc1 = "/rkvenc-core@fdbe0000";
		jpege0 = "/jpege-core@fdba0000";
		jpege1 = "/jpege-core@fdba4000";
		jpege2 = "/jpege-core@fdba8000";
		jpege3 = "/jpege-core@fdbac000";
		serial0 = "/serial@feb50000";
		serial1 = "/serial@febc0000";
		serial2 = "/serial@feb90000";
		serial3 = "/serial@feb60000";
		serial4 = "/serial@feb70000";
		serial5 = "/serial@feb80000";
		serial6 = "/serial@fd890000";
		serial7 = "/serial@feba0000";
		serial8 = "/serial@febb0000";
		serial9 = "/serial@feb40000";
		spi0 = "/spi@feb00000";
		spi1 = "/spi@feb10000";
		spi2 = "/spi@feb20000";
		spi3 = "/spi@feb30000";
		spi4 = "/spi@fecb0000";
		spi5 = "/spi@fe2b0000";
		hdcp0 = "/hdcp@fde40000";
		hdcp1 = "/hdcp@fde70000";
		mmc0 = "/mmc@fe2e0000";
		mmc1 = "/mmc@fe2d0000";
		mmc2 = "/mmc@fe2c0000";
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;

		spll {
			compatible = "fixed-clock";
			#clock-cells = <0x00>;
			clock-frequency = <0x29d7ab80>;
			clock-output-names = "spll";
		};

		xin32k {
			compatible = "fixed-clock";
			#clock-cells = <0x00>;
			clock-frequency = <0x8000>;
			clock-output-names = "xin32k";
		};

		xin24m {
			compatible = "fixed-clock";
			#clock-cells = <0x00>;
			clock-frequency = <0x16e3600>;
			clock-output-names = "xin24m";
		};

		hclk_vo1@fd7c08ec {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08ec 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x264>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
			phandle = <0x05>;
		};

		aclk_vdpu_low_pre@fd7c08b0 {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08b0 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x1bc>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		hclk_vo0@fd7c08dc {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08dc 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x26d>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
			phandle = <0x04>;
		};

		hclk_usb@fd7c08a8 {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08a8 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x264>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		hclk_nvm@fd7c087c {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c087c 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x141>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
			phandle = <0x03>;
		};

		aclk_usb@fd7c08a8 {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08a8 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x263>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		hclk_isp1_pre@fd7c0868 {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c0868 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x1e1>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		aclk_isp1_pre@fd7c0868 {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c0868 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x1e0>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		aclk_rkvdec0_pre@fd7c08a0 {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08a0 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x1bc>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		hclk_rkvdec0_pre@fd7c08a0 {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08a0 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x1be>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		aclk_rkvdec1_pre@fd7c08a4 {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08a4 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x1bc>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		hclk_rkvdec1_pre@fd7c08a4 {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08a4 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x1be>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		aclk_jpeg_decoder_pre@fd7c08b0 {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08b0 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x1bc>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		aclk_rkvenc1_pre@fd7c08c0 {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08c0 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x1c5>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		hclk_rkvenc1_pre@fd7c08c0 {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08c0 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x1c4>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		aclk_hdcp0_pre@fd7c08dc {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08dc 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x26c>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		aclk_hdcp1_pre@fd7c08ec {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08ec 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x263>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		pclk_av1_pre@fd7c0910 {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c0910 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x1be>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		aclk_av1_pre@fd7c0910 {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c0910 0x00 0x10>;
			clock-names = "link";
			clocks = <0x02 0x1bc>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		hclk_sdio_pre@fd7c092c {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c092c 0x00 0x10>;
			clock-names = "link";
			clocks = <0x03>;
			#power-domain-cells = <0x01>;
			#clock-cells = <0x00>;
		};

		pclk_vo0_grf@fd7c08dc {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08dc 0x00 0x04>;
			clocks = <0x04>;
			clock-names = "link";
			#clock-cells = <0x00>;
			phandle = <0x5e>;
		};

		pclk_vo1_grf@fd7c08ec {
			compatible = "rockchip,rk3588-clock-gate-link";
			reg = <0x00 0xfd7c08ec 0x00 0x04>;
			clocks = <0x05>;
			clock-names = "link";
			#clock-cells = <0x00>;
			phandle = <0x5f>;
		};
	};

	cpus {
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		cpu-map {

			cluster0 {

				core0 {
					cpu = <0x06>;
				};

				core1 {
					cpu = <0x07>;
				};

				core2 {
					cpu = <0x08>;
				};

				core3 {
					cpu = <0x09>;
				};
			};

			cluster1 {

				core0 {
					cpu = <0x0a>;
				};

				core1 {
					cpu = <0x0b>;
				};
			};

			cluster2 {

				core0 {
					cpu = <0x0c>;
				};

				core1 {
					cpu = <0x0d>;
				};
			};
		};

		cpu@400 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x400>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x400>;
			clocks = <0x0e 0x02>;
			operating-points-v2 = <0x0f>;
			cpu-idle-states = <0x10>;
			i-cache-size = <0x10000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x100>;
			d-cache-size = <0x10000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x100>;
			next-level-cache = <0x11>;
			#cooling-cells = <0x02>;
			dynamic-power-coefficient = <0x12c>;
			cpu-supply = <0x12>;
			mem-supply = <0x12>;
			phandle = <0x0a>;
		};

		cpu@500 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x500>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x400>;
			clocks = <0x0e 0x02>;
			operating-points-v2 = <0x0f>;
			cpu-idle-states = <0x10>;
			i-cache-size = <0x10000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x100>;
			d-cache-size = <0x10000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x100>;
			next-level-cache = <0x13>;
			phandle = <0x0b>;
		};

		cpu@600 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x600>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x400>;
			clocks = <0x0e 0x03>;
			operating-points-v2 = <0x14>;
			cpu-idle-states = <0x10>;
			i-cache-size = <0x10000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x100>;
			d-cache-size = <0x10000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x100>;
			next-level-cache = <0x15>;
			#cooling-cells = <0x02>;
			dynamic-power-coefficient = <0x12c>;
			cpu-supply = <0x16>;
			mem-supply = <0x16>;
			phandle = <0x0c>;
		};

		cpu@700 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x700>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x400>;
			clocks = <0x0e 0x03>;
			operating-points-v2 = <0x14>;
			cpu-idle-states = <0x10>;
			i-cache-size = <0x10000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x100>;
			d-cache-size = <0x10000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x100>;
			next-level-cache = <0x17>;
			phandle = <0x0d>;
		};

		idle-states {
			entry-method = "psci";

			cpu-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x10000>;
				entry-latency-us = <0x64>;
				exit-latency-us = <0x78>;
				min-residency-us = <0x3e8>;
				phandle = <0x10>;
			};
		};

		l2-cache-l0 {
			compatible = "cache";
			cache-size = <0x20000>;
			cache-line-size = <0x40>;
			cache-sets = <0x200>;
			next-level-cache = <0x18>;
			phandle = <0x1a>;
		};

		l2-cache-l1 {
			compatible = "cache";
			cache-size = <0x20000>;
			cache-line-size = <0x40>;
			cache-sets = <0x200>;
			next-level-cache = <0x18>;
			phandle = <0x1c>;
		};

		l2-cache-l2 {
			compatible = "cache";
			cache-size = <0x20000>;
			cache-line-size = <0x40>;
			cache-sets = <0x200>;
			next-level-cache = <0x18>;
			phandle = <0x1d>;
		};

		l2-cache-l3 {
			compatible = "cache";
			cache-size = <0x20000>;
			cache-line-size = <0x40>;
			cache-sets = <0x200>;
			next-level-cache = <0x18>;
			phandle = <0x1e>;
		};

		l2-cache-b0 {
			compatible = "cache";
			cache-size = <0x80000>;
			cache-line-size = <0x40>;
			cache-sets = <0x400>;
			next-level-cache = <0x18>;
			phandle = <0x11>;
		};

		l2-cache-b1 {
			compatible = "cache";
			cache-size = <0x80000>;
			cache-line-size = <0x40>;
			cache-sets = <0x400>;
			next-level-cache = <0x18>;
			phandle = <0x13>;
		};

		l2-cache-b2 {
			compatible = "cache";
			cache-size = <0x80000>;
			cache-line-size = <0x40>;
			cache-sets = <0x400>;
			next-level-cache = <0x18>;
			phandle = <0x15>;
		};

		l2-cache-b3 {
			compatible = "cache";
			cache-size = <0x80000>;
			cache-line-size = <0x40>;
			cache-sets = <0x400>;
			next-level-cache = <0x18>;
			phandle = <0x17>;
		};

		l3-cache {
			compatible = "cache";
			cache-size = <0x300000>;
			cache-line-size = <0x40>;
			cache-sets = <0x1000>;
			phandle = <0x18>;
		};

		cpu@0000 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x00>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x212>;
			clocks = <0x0e 0x00>;
			operating-points-v2 = <0x19>;
			cpu-idle-states = <0x10>;
			i-cache-size = <0x8000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x80>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x80>;
			next-level-cache = <0x1a>;
			#cooling-cells = <0x02>;
			dynamic-power-coefficient = <0xe4>;
			cpu-supply = <0x1b>;
			mem-supply = <0x1b>;
			phandle = <0x06>;
		};

		cpu@0100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x100>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x212>;
			clocks = <0x0e 0x00>;
			operating-points-v2 = <0x19>;
			cpu-idle-states = <0x10>;
			i-cache-size = <0x8000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x80>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x80>;
			next-level-cache = <0x1c>;
			phandle = <0x07>;
		};

		cpu@0200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x200>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x212>;
			clocks = <0x0e 0x00>;
			operating-points-v2 = <0x19>;
			cpu-idle-states = <0x10>;
			i-cache-size = <0x8000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x80>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x80>;
			next-level-cache = <0x1d>;
			phandle = <0x08>;
		};

		cpu@0300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x300>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x212>;
			clocks = <0x0e 0x00>;
			operating-points-v2 = <0x19>;
			cpu-idle-states = <0x10>;
			i-cache-size = <0x8000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x80>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x80>;
			next-level-cache = <0x1e>;
			phandle = <0x09>;
		};
	};

	cluster0-opp-table {
		compatible = "operating-points-v2";
		opp-shared;
		nvmem-cells = <0x1f 0x20>;
		nvmem-cell-names = "leakage\0specification_serial_number";
		rockchip,supported-hw;
		rockchip,opp-shared-dsu;
		rockchip,pvtm-voltage-sel = <0x00 0x582 0x00 0x583 0x59a 0x01 0x59b 0x5b2 0x02 0x5b3 0x5ca 0x03 0x5cb 0x5e2 0x04 0x5e3 0x5fa 0x05 0x5fb 0x270f 0x06>;
		rockchip,pvtm-pvtpll;
		rockchip,pvtm-offset = <0x64>;
		rockchip,pvtm-sample-time = <0x44c>;
		rockchip,pvtm-freq = <0x159b40>;
		rockchip,pvtm-volt = <0xb71b0>;
		rockchip,pvtm-ref-temp = <0x19>;
		rockchip,pvtm-temp-prop = <0xf4 0xf4>;
		rockchip,pvtm-thermal-zone = "soc-thermal";
		rockchip,grf = <0x21>;
		rockchip,dsu-grf = <0x22>;
		volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>;
		low-volt-mem-read-margin = <0x04>;
		intermediate-threshold-freq = <0xf6180>;
		rockchip,reboot-freq = <0x159b40>;
		rockchip,temp-hysteresis = <0x1388>;
		rockchip,low-temp = <0x2710>;
		rockchip,low-temp-min-volt = <0xb71b0>;
		rockchip,high-temp = <0x14c08>;
		rockchip,high-temp-max-freq = <0x188940>;
		phandle = <0x19>;

		opp-408000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x18519600>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
			clock-latency-ns = <0x9c40>;
		};

		opp-600000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
			clock-latency-ns = <0x9c40>;
		};

		opp-816000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x30a32c00>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1008000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x3c14dc00>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1200000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x47868c00>;
			opp-microvolt = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>;
			opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>;
			opp-microvolt-L2 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>;
			opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>;
			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
			opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1416000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x54667200>;
			opp-microvolt = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>;
			opp-microvolt-L1 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
			opp-microvolt-L2 = <0xb40dc 0xb40dc 0xe7ef0 0xb40dc 0xb40dc 0xe7ef0>;
			opp-microvolt-L3 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>;
			opp-microvolt-L4 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>;
			opp-microvolt-L5 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>;
			opp-microvolt-L6 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>;
			clock-latency-ns = <0x9c40>;
			opp-suspend;
		};

		opp-1608000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x5fd82200>;
			opp-microvolt = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>;
			opp-microvolt-L1 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>;
			opp-microvolt-L2 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>;
			opp-microvolt-L3 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>;
			opp-microvolt-L4 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>;
			opp-microvolt-L5 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>;
			opp-microvolt-L6 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1704000000 {
			opp-supported-hw = <0x02 0xffff>;
			opp-hz = <0x00 0x6590fa00>;
			opp-microvolt = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>;
			opp-microvolt-L1 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>;
			opp-microvolt-L2 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>;
			opp-microvolt-L3 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>;
			opp-microvolt-L4 = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>;
			opp-microvolt-L5 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>;
			opp-microvolt-L6 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1800000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = <0x00 0x6b49d200>;
			opp-microvolt = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>;
			opp-microvolt-L1 = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>;
			opp-microvolt-L2 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>;
			opp-microvolt-L3 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>;
			opp-microvolt-L4 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>;
			opp-microvolt-L5 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>;
			opp-microvolt-L6 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>;
			clock-latency-ns = <0x9c40>;
		};
	};

	cluster1-opp-table {
		compatible = "operating-points-v2";
		opp-shared;
		nvmem-cells = <0x23 0x20>;
		nvmem-cell-names = "leakage\0specification_serial_number";
		rockchip,supported-hw;
		rockchip,pvtm-voltage-sel = <0x00 0x63b 0x00 0x63c 0x64f 0x01 0x650 0x668 0x02 0x669 0x68b 0x03 0x68c 0x6ae 0x04 0x6af 0x6cf 0x05 0x6d0 0x6f0 0x06 0x6f1 0x270f 0x07>;
		rockchip,pvtm-pvtpll;
		rockchip,pvtm-offset = <0x18>;
		rockchip,pvtm-sample-time = <0x44c>;
		rockchip,pvtm-freq = <0x188940>;
		rockchip,pvtm-volt = <0xb71b0>;
		rockchip,pvtm-ref-temp = <0x19>;
		rockchip,pvtm-temp-prop = <0x10e 0x10e>;
		rockchip,pvtm-thermal-zone = "soc-thermal";
		rockchip,pvtm-low-len-sel = <0x03>;
		rockchip,grf = <0x24>;
		volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>;
		low-volt-mem-read-margin = <0x04>;
		intermediate-threshold-freq = <0xf6180>;
		rockchip,idle-threshold-freq = <0x21b100>;
		rockchip,reboot-freq = <0x1b7740>;
		rockchip,temp-hysteresis = <0x1388>;
		rockchip,low-temp = <0x2710>;
		rockchip,low-temp-min-volt = <0xb71b0>;
		rockchip,high-temp = <0x14c08>;
		rockchip,high-temp-max-freq = <0x21b100>;
		phandle = <0x0f>;

		opp-408000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x18519600>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
			clock-latency-ns = <0x9c40>;
			opp-suspend;
		};

		opp-600000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-816000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x30a32c00>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1008000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x3c14dc00>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1200000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x47868c00>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1416000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x54667200>;
			opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
			opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
			opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
			opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
			opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>;
			opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
			opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1608000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x5fd82200>;
			opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
			opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>;
			opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>;
			opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
			opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
			opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
			opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1800000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x6b49d200>;
			opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
			opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
			opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>;
			opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>;
			opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>;
			opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>;
			opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>;
			opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-2016000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x7829b800>;
			opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
			opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
			opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>;
			opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>;
			opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>;
			opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>;
			opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
			opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-2208000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = <0x00 0x839b6800>;
			opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>;
			opp-microvolt-L1 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>;
			opp-microvolt-L2 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>;
			opp-microvolt-L3 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>;
			opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>;
			opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>;
			opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
			opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-2256000000 {
			opp-supported-hw = <0xf9 0x13>;
			opp-hz = <0x00 0x8677d400>;
			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-2304000000 {
			opp-supported-hw = <0xf9 0x24>;
			opp-hz = <0x00 0x89544000>;
			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-2352000000 {
			opp-supported-hw = <0xf9 0x48>;
			opp-hz = <0x00 0x8c30ac00>;
			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-2400000000 {
			opp-supported-hw = <0xf9 0x80>;
			opp-hz = <0x00 0x8f0d1800>;
			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};
	};

	cluster2-opp-table {
		compatible = "operating-points-v2";
		opp-shared;
		nvmem-cells = <0x25 0x20>;
		nvmem-cell-names = "leakage\0specification_serial_number";
		rockchip,supported-hw;
		rockchip,pvtm-voltage-sel = <0x00 0x63b 0x00 0x63c 0x64f 0x01 0x650 0x668 0x02 0x669 0x68b 0x03 0x68c 0x6ae 0x04 0x6af 0x6cf 0x05 0x6d0 0x6f0 0x06 0x6f1 0x270f 0x07>;
		rockchip,pvtm-pvtpll;
		rockchip,pvtm-offset = <0x18>;
		rockchip,pvtm-sample-time = <0x44c>;
		rockchip,pvtm-freq = <0x188940>;
		rockchip,pvtm-volt = <0xb71b0>;
		rockchip,pvtm-ref-temp = <0x19>;
		rockchip,pvtm-temp-prop = <0x10e 0x10e>;
		rockchip,pvtm-thermal-zone = "soc-thermal";
		rockchip,pvtm-low-len-sel = <0x03>;
		rockchip,grf = <0x26>;
		volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>;
		low-volt-mem-read-margin = <0x04>;
		intermediate-threshold-freq = <0xf6180>;
		rockchip,idle-threshold-freq = <0x21b100>;
		rockchip,reboot-freq = <0x1b7740>;
		rockchip,temp-hysteresis = <0x1388>;
		rockchip,low-temp = <0x2710>;
		rockchip,low-temp-min-volt = <0xb71b0>;
		rockchip,high-temp = <0x14c08>;
		rockchip,high-temp-max-freq = <0x21b100>;
		phandle = <0x14>;

		opp-408000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x18519600>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
			clock-latency-ns = <0x9c40>;
			opp-suspend;
		};

		opp-600000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-816000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x30a32c00>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1008000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x3c14dc00>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1200000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x47868c00>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1416000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x54667200>;
			opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
			opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
			opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
			opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
			opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>;
			opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
			opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1608000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x5fd82200>;
			opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
			opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>;
			opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>;
			opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
			opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
			opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
			opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1800000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x6b49d200>;
			opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
			opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
			opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>;
			opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>;
			opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>;
			opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>;
			opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>;
			opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-2016000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x7829b800>;
			opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
			opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
			opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>;
			opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>;
			opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>;
			opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>;
			opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
			opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-2208000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = <0x00 0x839b6800>;
			opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>;
			opp-microvolt-L3 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>;
			opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>;
			opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>;
			opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
			opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-2256000000 {
			opp-supported-hw = <0xf9 0x13>;
			opp-hz = <0x00 0x8677d400>;
			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-2304000000 {
			opp-supported-hw = <0xf9 0x24>;
			opp-hz = <0x00 0x89544000>;
			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-2352000000 {
			opp-supported-hw = <0xf9 0x48>;
			opp-hz = <0x00 0x8c30ac00>;
			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};

		opp-2400000000 {
			opp-supported-hw = <0xf9 0x80>;
			opp-hz = <0x00 0x8f0d1800>;
			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
			clock-latency-ns = <0x9c40>;
		};
	};

	arm-pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <0x01 0x07 0x08>;
		interrupt-affinity = <0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d>;
	};

	cpuinfo {
		compatible = "rockchip,cpuinfo";
		nvmem-cells = <0x27 0x28 0x29>;
		nvmem-cell-names = "id\0cpu-version\0cpu-code";
	};

	csi2-dcphy0 {
		compatible = "rockchip,rk3588-csi2-dcphy";
		phys = <0x2a>;
		phy-names = "dcphy";
		status = "disabled";
	};

	csi2-dcphy1 {
		compatible = "rockchip,rk3588-csi2-dcphy";
		phys = <0x2b>;
		phy-names = "dcphy";
		status = "disabled";
	};

	csi2-dphy0 {
		compatible = "rockchip,rk3568-csi2-dphy";
		rockchip,hw = <0x2c>;
		status = "okay";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0x2d>;
					data-lanes = <0x01 0x02>;
					phandle = <0x15a>;
				};

				endpoint@2 {
					reg = <0x02>;
					remote-endpoint = <0x2e>;
					data-lanes = <0x01 0x02>;
					phandle = <0x15b>;
				};

				endpoint@3 {
					reg = <0x03>;
					remote-endpoint = <0x2f>;
					data-lanes = <0x01 0x02>;
					phandle = <0x15c>;
				};
			};

			port@1 {
				reg = <0x01>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0x30>;
					phandle = <0xba>;
				};
			};
		};
	};

	csi2-dphy1 {
		compatible = "rockchip,rk3568-csi2-dphy";
		rockchip,hw = <0x2c>;
		status = "disabled";
	};

	csi2-dphy2 {
		compatible = "rockchip,rk3568-csi2-dphy";
		rockchip,hw = <0x2c>;
		status = "disabled";
	};

	display-subsystem {
		compatible = "rockchip,display-subsystem";
		ports = <0x31>;
		clocks = <0x32>;
		clock-names = "hdmi0_phy_pll";
		memory-region = <0x33>;
		memory-region-names = "drm-logo";

		route {

			route-dp0 {
				status = "disabled";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <0x34>;
			};

			route-dsi0 {
				status = "disabled";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <0x35>;
			};

			route-dsi1 {
				status = "disabled";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <0x36>;
			};

			route-edp0 {
				status = "disabled";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <0x37>;
			};

			route-edp1 {
				status = "disabled";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
			};

			route-hdmi0 {
				status = "okay";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <0x38>;
			};

			route-rgb {
				status = "disabled";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <0x39>;
			};
		};
	};

	dmc {
		compatible = "rockchip,rk3588-dmc";
		interrupts = <0x00 0x49 0x04>;
		interrupt-names = "complete";
		devfreq-events = <0x3a>;
		clocks = <0x0e 0x04>;
		clock-names = "dmc_clk";
		operating-points-v2 = <0x3b>;
		upthreshold = <0x28>;
		downdifferential = <0x14>;
		system-status-level = <0x01 0x04 0x08 0x08 0x02 0x01 0x10 0x04 0x10000 0x04 0x80000 0x04 0x1000 0x08 0x4000 0x08 0x2000 0x08 0xc00 0x08 0x40000 0x08>;
		auto-freq-en = <0x01>;
		status = "disabled";
	};

	dmc-opp-table {
		compatible = "operating-points-v2";
		nvmem-cells = <0x3c>;
		nvmem-cell-names = "leakage";
		rockchip,leakage-voltage-sel = <0x01 0x1f 0x00 0x20 0x2c 0x01 0x2d 0x39 0x02 0x3a 0xfe 0x03>;
		rockchip,temp-hysteresis = <0x1388>;
		rockchip,low-temp = <0x2710>;
		rockchip,low-temp-min-volt = <0xb71b0>;
		phandle = <0x3b>;

		opp-528000000 {
			opp-hz = <0x00 0x1f78a400>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xd59f8 0xb1008 0xb1008 0xb71b0>;
			opp-microvolt-L1 = <0xa4cb8 0xa4cb8 0xd59f8 0xaae60 0xaae60 0xb71b0>;
			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xd59f8 0xa7d8c 0xa7d8c 0xb71b0>;
			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xd59f8 0xa4cb8 0xa4cb8 0xb71b0>;
		};

		opp-1068000000 {
			opp-hz = <0x00 0x3fa86300>;
			opp-microvolt = <0xb1008 0xb1008 0xd59f8 0xb40dc 0xb40dc 0xb71b0>;
			opp-microvolt-L1 = <0xaae60 0xaae60 0xd59f8 0xadf34 0xadf34 0xb71b0>;
			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xd59f8 0xaae60 0xaae60 0xb71b0>;
			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xd59f8 0xa7d8c 0xa7d8c 0xb71b0>;
		};

		opp-1560000000 {
			opp-hz = <0x00 0x5cfbb600>;
			opp-microvolt = <0xc3500 0xc3500 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
			opp-microvolt-L1 = <0xbd358 0xbd358 0xd59f8 0xb1008 0xb1008 0xb71b0>;
			opp-microvolt-L2 = <0xb71b0 0xb71b0 0xd59f8 0xadf34 0xadf34 0xb71b0>;
			opp-microvolt-L3 = <0xb1008 0xb1008 0xd59f8 0xaae60 0xaae60 0xb71b0>;
		};

		opp-2750000000 {
			opp-hz = <0x00 0xa3e9ab80>;
			opp-microvolt = <0xd59f8 0xd59f8 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
			opp-microvolt-L1 = <0xcf850 0xcf850 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
			opp-microvolt-L2 = <0xcc77c 0xcc77c 0xd59f8 0xb1008 0xb1008 0xb71b0>;
			opp-microvolt-L3 = <0xc96a8 0xc8320 0xd59f8 0xaae60 0xaae60 0xb71b0>;
		};
	};

	firmware {

		scmi {
			compatible = "arm,scmi-smc";
			shmem = <0x3d>;
			arm,smc-id = <0x82000010>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			protocol@14 {
				reg = <0x14>;
				#clock-cells = <0x01>;
				assigned-clocks = <0x0e 0x00 0x0e 0x02 0x0e 0x03>;
				assigned-clock-rates = <0x30a32c00 0x30a32c00 0x30a32c00>;
				phandle = <0x0e>;
			};

			protocol@16 {
				reg = <0x16>;
				#reset-cells = <0x01>;
				phandle = <0xf9>;
			};
		};

		sdei {
			compatible = "arm,sdei-1.0";
			method = "smc";
		};

		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

	jpege-ccu {
		compatible = "rockchip,vpu-jpege-ccu";
		status = "okay";
		phandle = <0xa6>;
	};

	mpp-srv {
		compatible = "rockchip,mpp-service";
		rockchip,taskqueue-count = <0x0c>;
		rockchip,resetgroup-count = <0x01>;
		status = "okay";
		phandle = <0xa1>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	rkcif-dvp {
		compatible = "rockchip,rkcif-dvp";
		rockchip,hw = <0x3e>;
		iommus = <0x3f>;
		status = "disabled";
		phandle = <0x40>;
	};

	rkcif-dvp-sditf {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x40>;
		status = "disabled";
	};

	rkcif-mipi-lvds {
		compatible = "rockchip,rkcif-mipi-lvds";
		rockchip,hw = <0x3e>;
		iommus = <0x3f>;
		status = "disabled";
		phandle = <0x41>;
	};

	rkcif-mipi-lvds-sditf {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x41>;
		status = "disabled";
	};

	rkcif-mipi-lvds-sditf-vir1 {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x41>;
		status = "disabled";
	};

	rkcif-mipi-lvds-sditf-vir2 {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x41>;
		status = "disabled";
	};

	rkcif-mipi-lvds-sditf-vir3 {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x41>;
		status = "disabled";
	};

	rkcif-mipi-lvds1 {
		compatible = "rockchip,rkcif-mipi-lvds";
		rockchip,hw = <0x3e>;
		iommus = <0x3f>;
		status = "disabled";
		phandle = <0x42>;
	};

	rkcif-mipi-lvds1-sditf {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x42>;
		status = "disabled";
	};

	rkcif-mipi-lvds1-sditf-vir1 {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x42>;
		status = "disabled";
	};

	rkcif-mipi-lvds1-sditf-vir2 {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x42>;
		status = "disabled";
	};

	rkcif-mipi-lvds1-sditf-vir3 {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x42>;
		status = "disabled";
	};

	rkcif-mipi-lvds2 {
		compatible = "rockchip,rkcif-mipi-lvds";
		rockchip,hw = <0x3e>;
		iommus = <0x3f>;
		status = "okay";
		phandle = <0x44>;

		port {

			endpoint {
				remote-endpoint = <0x43>;
				phandle = <0xbb>;
			};
		};
	};

	rkcif-mipi-lvds2-sditf {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x44>;
		status = "okay";

		port {

			endpoint {
				remote-endpoint = <0x45>;
				phandle = <0x48>;
			};
		};
	};

	rkcif-mipi-lvds2-sditf-vir1 {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x44>;
		status = "disabled";
	};

	rkcif-mipi-lvds2-sditf-vir2 {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x44>;
		status = "disabled";
	};

	rkcif-mipi-lvds2-sditf-vir3 {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x44>;
		status = "disabled";
	};

	rkcif-mipi-lvds3 {
		compatible = "rockchip,rkcif-mipi-lvds";
		rockchip,hw = <0x3e>;
		iommus = <0x3f>;
		status = "disabled";
		phandle = <0x46>;
	};

	rkcif-mipi-lvds3-sditf {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x46>;
		status = "disabled";
	};

	rkcif-mipi-lvds3-sditf-vir1 {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x46>;
		status = "disabled";
	};

	rkcif-mipi-lvds3-sditf-vir2 {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x46>;
		status = "disabled";
	};

	rkcif-mipi-lvds3-sditf-vir3 {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x46>;
		status = "disabled";
	};

	rkisp0-vir0 {
		compatible = "rockchip,rkisp-vir";
		rockchip,hw = <0x47>;
		status = "okay";

		port {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			endpoint@0 {
				reg = <0x00>;
				remote-endpoint = <0x48>;
				phandle = <0x45>;
			};
		};
	};

	rkisp0-vir1 {
		compatible = "rockchip,rkisp-vir";
		rockchip,hw = <0x47>;
		status = "disabled";
	};

	rkisp0-vir2 {
		compatible = "rockchip,rkisp-vir";
		rockchip,hw = <0x47>;
		status = "disabled";
	};

	rkisp0-vir3 {
		compatible = "rockchip,rkisp-vir";
		rockchip,hw = <0x47>;
		status = "disabled";
	};

	rkisp1-vir0 {
		compatible = "rockchip,rkisp-vir";
		rockchip,hw = <0x49>;
		status = "disabled";
	};

	rkisp1-vir1 {
		compatible = "rockchip,rkisp-vir";
		rockchip,hw = <0x49>;
		status = "disabled";
	};

	rkisp1-vir2 {
		compatible = "rockchip,rkisp-vir";
		rockchip,hw = <0x49>;
		status = "disabled";
	};

	rkisp1-vir3 {
		compatible = "rockchip,rkisp-vir";
		rockchip,hw = <0x49>;
		status = "disabled";
	};

	rkispp0-vir0 {
		compatible = "rockchip,rk3588-rkispp-vir";
		rockchip,hw = <0x4a>;
		status = "disabled";
	};

	rkispp1-vir0 {
		compatible = "rockchip,rk3588-rkispp-vir";
		rockchip,hw = <0x4b>;
		status = "disabled";
	};

	rkvenc-ccu {
		compatible = "rockchip,rkv-encoder-v2-ccu";
		status = "okay";
		phandle = <0xac>;
	};

	rockchip-suspend {
		compatible = "rockchip,pm-rk3588";
		status = "okay";
		rockchip,sleep-debug-en = <0x01>;
		rockchip,sleep-mode-config = <0x1000608>;
		rockchip,wakeup-config = <0x100>;
	};

	rockchip-system-monitor {
		compatible = "rockchip,system-monitor";
		rockchip,thermal-zone = "soc-thermal";
	};

	thermal-zones {

		soc-thermal {
			polling-delay-passive = <0x14>;
			polling-delay = <0x3e8>;
			sustainable-power = <0x834>;
			thermal-sensors = <0x4c 0x00>;

			trips {

				trip-point-0 {
					temperature = <0x124f8>;
					hysteresis = <0x7d0>;
					type = "passive";
				};

				trip-point-1 {
					temperature = <0x14c08>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0x4d>;
				};

				soc-crit {
					temperature = <0x1c138>;
					hysteresis = <0x7d0>;
					type = "critical";
				};
			};

			cooling-maps {

				map0 {
					trip = <0x4d>;
					cooling-device = <0x06 0xffffffff 0xffffffff>;
					contribution = <0x400>;
				};

				map1 {
					trip = <0x4d>;
					cooling-device = <0x0a 0xffffffff 0xffffffff>;
					contribution = <0x400>;
				};

				map2 {
					trip = <0x4d>;
					cooling-device = <0x0c 0xffffffff 0xffffffff>;
					contribution = <0x400>;
				};

				map3 {
					trip = <0x4d>;
					cooling-device = <0x4e 0xffffffff 0xffffffff>;
					contribution = <0x400>;
				};
			};
		};

		bigcore0-thermal {
			polling-delay-passive = <0x14>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0x4c 0x01>;
		};

		bigcore1-thermal {
			polling-delay-passive = <0x14>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0x4c 0x02>;
		};

		littlecore-thermal {
			polling-delay-passive = <0x14>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0x4c 0x03>;
		};

		center-thermal {
			polling-delay-passive = <0x14>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0x4c 0x04>;
		};

		gpu-thermal {
			polling-delay-passive = <0x14>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0x4c 0x05>;
		};

		npu-thermal {
			polling-delay-passive = <0x14>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0x4c 0x06>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>;
	};

	sram@10f000 {
		compatible = "mmio-sram";
		reg = <0x00 0x10f000 0x00 0x100>;
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		ranges = <0x00 0x00 0x10f000 0x100>;

		sram@0 {
			compatible = "arm,scmi-shmem";
			reg = <0x00 0x100>;
			phandle = <0x3d>;
		};
	};

	gpu@fb000000 {
		compatible = "arm,mali-bifrost";
		reg = <0x00 0xfb000000 0x00 0x200000>;
		interrupts = <0x00 0x5e 0x04 0x00 0x5d 0x04 0x00 0x5c 0x04>;
		interrupt-names = "GPU\0MMU\0JOB";
		clocks = <0x0e 0x05 0x02 0x115 0x02 0x116 0x02 0x114>;
		clock-names = "clk_mali\0clk_gpu_coregroup\0clk_gpu_stacks\0clk_gpu";
		assigned-clocks = <0x0e 0x05>;
		assigned-clock-rates = <0xbebc200>;
		power-domains = <0x4f 0x0c>;
		operating-points-v2 = <0x50>;
		#cooling-cells = <0x02>;
		dynamic-power-coefficient = <0xba6>;
		upthreshold = <0x1e>;
		downdifferential = <0x0a>;
		status = "okay";
		mali-supply = <0x51>;
		mem-supply = <0x51>;
		phandle = <0x4e>;
	};

	gpu-opp-table {
		compatible = "operating-points-v2";
		nvmem-cells = <0x52 0x20>;
		nvmem-cell-names = "leakage\0specification_serial_number";
		rockchip,supported-hw;
		rockchip,pvtm-voltage-sel = <0x00 0x32f 0x00 0x330 0x343 0x01 0x344 0x35c 0x02 0x35d 0x375 0x03 0x376 0x38e 0x04 0x38f 0x270f 0x05>;
		rockchip,pvtm-pvtpll;
		rockchip,pvtm-offset = <0x1c>;
		rockchip,pvtm-sample-time = <0x44c>;
		rockchip,pvtm-freq = "\0\f5";
		rockchip,pvtm-volt = <0xb71b0>;
		rockchip,pvtm-ref-temp = <0x19>;
		rockchip,pvtm-temp-prop = <0xffffff79 0xffffff79>;
		rockchip,pvtm-thermal-zone = "gpu-thermal";
		clocks = <0x02 0x114>;
		clock-names = "clk";
		rockchip,grf = <0x53>;
		volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>;
		low-volt-mem-read-margin = <0x04>;
		intermediate-threshold-freq = <0x61a80>;
		rockchip,temp-hysteresis = <0x1388>;
		rockchip,low-temp = <0x2710>;
		rockchip,low-temp-min-volt = <0xb71b0>;
		rockchip,high-temp = <0x14c08>;
		rockchip,high-temp-max-freq = "\0\f5";
		phandle = <0x50>;

		opp-300000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x11e1a300>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
		};

		opp-400000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x17d78400>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
		};

		opp-500000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x1dcd6500>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
		};

		opp-600000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
		};

		opp-700000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x29b92700>;
			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
			opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
		};

		opp-800000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x2faf0800>;
			opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
			opp-microvolt-L1 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>;
			opp-microvolt-L2 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>;
			opp-microvolt-L3 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>;
			opp-microvolt-L4 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
			opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
		};

		opp-900000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x35a4e900>;
			opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
			opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
			opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>;
			opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>;
			opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
			opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>;
		};

		opp-1000000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x3b9aca00>;
			opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>;
			opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>;
			opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>;
			opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>;
			opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
			opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
		};
	};

	usbdrd3_0 {
		compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3";
		clocks = <0x02 0x1a3 0x02 0x1a2 0x02 0x1a1>;
		clock-names = "ref\0suspend\0bus";
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		status = "okay";

		usb@fc000000 {
			compatible = "snps,dwc3";
			reg = <0x00 0xfc000000 0x00 0x400000>;
			interrupts = <0x00 0xdc 0x04>;
			power-domains = <0x4f 0x1f>;
			resets = <0x02 0x2a4>;
			reset-names = "usb3-otg";
			dr_mode = "host";
			phys = <0x54 0x55>;
			phy-names = "usb2-phy\0usb3-phy";
			phy_type = "utmi_wide";
			snps,dis_enblslpm_quirk;
			snps,dis-u1-entry-quirk;
			snps,dis-u2-entry-quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,dis-tx-ipgap-linecheck-quirk;
			snps,parkmode-disable-ss-quirk;
			quirk-skip-phy-init;
			status = "okay";
		};
	};

	usb@fc800000 {
		compatible = "rockchip,rk3588-ehci\0generic-ehci";
		reg = <0x00 0xfc800000 0x00 0x40000>;
		interrupts = <0x00 0xd7 0x04>;
		clocks = <0x02 0x19d 0x02 0x19e 0x56>;
		clock-names = "usbhost\0arbiter\0utmi";
		companion = <0x57>;
		phys = <0x58>;
		phy-names = "usb2-phy";
		power-domains = <0x4f 0x1f>;
		status = "okay";
	};

	usb@fc840000 {
		compatible = "generic-ohci";
		reg = <0x00 0xfc840000 0x00 0x40000>;
		interrupts = <0x00 0xd8 0x04>;
		clocks = <0x02 0x19d 0x02 0x19e 0x56>;
		clock-names = "usbhost\0arbiter\0utmi";
		phys = <0x58>;
		phy-names = "usb2-phy";
		power-domains = <0x4f 0x1f>;
		status = "okay";
		phandle = <0x57>;
	};

	usb@fc880000 {
		compatible = "rockchip,rk3588-ehci\0generic-ehci";
		reg = <0x00 0xfc880000 0x00 0x40000>;
		interrupts = <0x00 0xda 0x04>;
		clocks = <0x02 0x19f 0x02 0x1a0 0x59>;
		clock-names = "usbhost\0arbiter\0utmi";
		companion = <0x5a>;
		phys = <0x5b>;
		phy-names = "usb2-phy";
		power-domains = <0x4f 0x1f>;
		status = "okay";
	};

	usb@fc8c0000 {
		compatible = "generic-ohci";
		reg = <0x00 0xfc8c0000 0x00 0x40000>;
		interrupts = <0x00 0xdb 0x04>;
		clocks = <0x02 0x19f 0x02 0x1a0 0x59>;
		clock-names = "usbhost\0arbiter\0utmi";
		phys = <0x5b>;
		phy-names = "usb2-phy";
		power-domains = <0x4f 0x1f>;
		status = "okay";
		phandle = <0x5a>;
	};

	iommu@fc900000 {
		compatible = "arm,smmu-v3";
		reg = <0x00 0xfc900000 0x00 0x200000>;
		interrupts = <0x00 0x171 0x04 0x00 0x173 0x04 0x00 0x176 0x04 0x00 0x16f 0x04>;
		interrupt-names = "eventq\0gerror\0priq\0cmdq-sync";
		#iommu-cells = <0x01>;
		status = "disabled";
	};

	iommu@fcb00000 {
		compatible = "arm,smmu-v3";
		reg = <0x00 0xfcb00000 0x00 0x200000>;
		interrupts = <0x00 0x17d 0x04 0x00 0x17f 0x04 0x00 0x182 0x04 0x00 0x17b 0x04>;
		interrupt-names = "eventq\0gerror\0priq\0cmdq-sync";
		#iommu-cells = <0x01>;
		status = "disabled";
	};

	usbhost3_0 {
		compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3";
		clocks = <0x02 0x179 0x02 0x178 0x02 0x177 0x02 0x17a 0x02 0x166 0x02 0x181>;
		clock-names = "ref\0suspend\0bus\0utmi\0php\0pipe";
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		status = "okay";

		usb@fcd00000 {
			compatible = "snps,dwc3";
			reg = <0x00 0xfcd00000 0x00 0x400000>;
			interrupts = <0x00 0xde 0x04>;
			resets = <0x02 0x237>;
			reset-names = "usb3-host";
			dr_mode = "host";
			phys = <0x5c 0x04>;
			phy-names = "usb3-phy";
			phy_type = "utmi_wide";
			snps,dis_enblslpm_quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,dis-tx-ipgap-linecheck-quirk;
			snps,dis_rxdet_inp3_quirk;
			snps,parkmode-disable-ss-quirk;
			status = "okay";
		};
	};

	syscon@fd588000 {
		compatible = "rockchip,rk3588-pmu0-grf\0syscon\0simple-mfd";
		reg = <0x00 0xfd588000 0x00 0x2000>;

		reboot-mode {
			compatible = "syscon-reboot-mode";
			offset = <0x80>;
			mode-bootloader = <0x5242c301>;
			mode-charge = <0x5242c30b>;
			mode-fastboot = <0x5242c309>;
			mode-loader = <0x5242c301>;
			mode-normal = <0x5242c300>;
			mode-recovery = <0x5242c303>;
			mode-ums = <0x5242c30c>;
			mode-panic = <0x5242c307>;
			mode-watchdog = <0x5242c308>;
		};
	};

	syscon@fd58a000 {
		compatible = "rockchip,rk3588-pmu1-grf\0syscon";
		reg = <0x00 0xfd58a000 0x00 0x2000>;
		phandle = <0xe6>;
	};

	syscon@fd58c000 {
		compatible = "rockchip,rk3588-sys-grf\0syscon\0simple-mfd";
		reg = <0x00 0xfd58c000 0x00 0x1000>;
		phandle = <0xb9>;

		rgb {
			compatible = "rockchip,rk3588-rgb";
			pinctrl-names = "default";
			pinctrl-0 = <0x5d>;
			status = "disabled";

			ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				port@0 {
					reg = <0x00>;
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					endpoint@2 {
						reg = <0x02>;
						remote-endpoint = <0x39>;
						status = "disabled";
						phandle = <0xcd>;
					};
				};
			};
		};
	};

	syscon@fd590000 {
		compatible = "rockchip,rk3588-bigcore0-grf\0syscon";
		reg = <0x00 0xfd590000 0x00 0x100>;
		phandle = <0x24>;
	};

	syscon@fd592000 {
		compatible = "rockchip,rk3588-bigcore1-grf\0syscon";
		reg = <0x00 0xfd592000 0x00 0x100>;
		phandle = <0x26>;
	};

	syscon@fd594000 {
		compatible = "rockchip,rk3588-litcore-grf\0syscon";
		reg = <0x00 0xfd594000 0x00 0x100>;
		phandle = <0x21>;
	};

	syscon@fd598000 {
		compatible = "rockchip,rk3588-dsu-grf\0syscon";
		reg = <0x00 0xfd598000 0x00 0x100>;
		phandle = <0x22>;
	};

	syscon@fd5a0000 {
		compatible = "rockchip,rk3588-gpu-grf\0syscon";
		reg = <0x00 0xfd5a0000 0x00 0x100>;
		phandle = <0x53>;
	};

	syscon@fd5a2000 {
		compatible = "rockchip,rk3588-npu-grf\0syscon";
		reg = <0x00 0xfd5a2000 0x00 0x100>;
		phandle = <0x9f>;
	};

	syscon@fd5a4000 {
		compatible = "rockchip,rk3588-vop-grf\0syscon";
		reg = <0x00 0xfd5a4000 0x00 0x2000>;
		phandle = <0xbd>;
	};

	syscon@fd5a6000 {
		compatible = "rockchip,rk3588-vo-grf\0syscon";
		reg = <0x00 0xfd5a6000 0x00 0x2000>;
		clocks = <0x5e>;
		phandle = <0xd6>;
	};

	syscon@fd5a8000 {
		compatible = "rockchip,rk3588-vo-grf\0syscon";
		reg = <0x00 0xfd5a8000 0x00 0x100>;
		clocks = <0x5f>;
		phandle = <0xbe>;
	};

	syscon@fd5ac000 {
		compatible = "rockchip,rk3588-usb-grf\0syscon";
		reg = <0x00 0xfd5ac000 0x00 0x4000>;
		phandle = <0x60>;
	};

	syscon@fd5b0000 {
		compatible = "rockchip,rk3588-php-grf\0syscon";
		reg = <0x00 0xfd5b0000 0x00 0x1000>;
		phandle = <0x63>;
	};

	syscon@fd5b4000 {
		compatible = "rockchip,mipi-dphy-grf\0syscon";
		reg = <0x00 0xfd5b4000 0x00 0x1000>;
		phandle = <0x166>;
	};

	syscon@fd5b5000 {
		compatible = "rockchip,mipi-dphy-grf\0syscon";
		reg = <0x00 0xfd5b5000 0x00 0x1000>;
	};

	syscon@fd5bc000 {
		compatible = "rockchip,pipe-phy-grf\0syscon";
		reg = <0x00 0xfd5bc000 0x00 0x100>;
		phandle = <0x167>;
	};

	syscon@fd5c4000 {
		compatible = "rockchip,pipe-phy-grf\0syscon";
		reg = <0x00 0xfd5c4000 0x00 0x100>;
		phandle = <0x168>;
	};

	syscon@fd5c8000 {
		compatible = "rockchip,rk3588-usbdpphy-grf\0syscon";
		reg = <0x00 0xfd5c8000 0x00 0x4000>;
		phandle = <0x162>;
	};

	syscon@fd5d0000 {
		compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd";
		reg = <0x00 0xfd5d0000 0x00 0x4000>;
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		phandle = <0x161>;

		usb2-phy@0 {
			compatible = "rockchip,rk3588-usb2phy";
			reg = <0x00 0x10>;
			interrupts = <0x00 0x189 0x04>;
			resets = <0x02 0xc0047 0x02 0x488>;
			reset-names = "phy\0apb";
			clocks = <0x02 0x2b5>;
			clock-names = "phyclk";
			clock-output-names = "usb480m_phy0";
			#clock-cells = <0x00>;
			rockchip,usbctrl-grf = <0x60>;
			status = "okay";
			phandle = <0x163>;

			otg-port {
				#phy-cells = <0x00>;
				status = "okay";
				vbus-supply = <0x61>;
				phandle = <0x54>;
			};
		};
	};

	syscon@fd5d8000 {
		compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd";
		reg = <0x00 0xfd5d8000 0x00 0x4000>;
		#address-cells = <0x01>;
		#size-cells = <0x01>;

		usb2-phy@8000 {
			compatible = "rockchip,rk3588-usb2phy";
			reg = <0x8000 0x10>;
			interrupts = <0x00 0x187 0x04>;
			resets = <0x02 0xc0049 0x02 0x48a>;
			reset-names = "phy\0apb";
			clocks = <0x02 0x2b5>;
			clock-names = "phyclk";
			clock-output-names = "usb480m_phy2";
			#clock-cells = <0x00>;
			status = "okay";
			phandle = <0x56>;

			host-port {
				#phy-cells = <0x00>;
				status = "okay";
				phy-supply = <0x62>;
				phandle = <0x58>;
			};
		};
	};

	syscon@fd5dc000 {
		compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd";
		reg = <0x00 0xfd5dc000 0x00 0x4000>;
		#address-cells = <0x01>;
		#size-cells = <0x01>;

		usb2-phy@c000 {
			compatible = "rockchip,rk3588-usb2phy";
			reg = <0xc000 0x10>;
			interrupts = <0x00 0x188 0x04>;
			resets = <0x02 0xc004a 0x02 0x48b>;
			reset-names = "phy\0apb";
			clocks = <0x02 0x2b5>;
			clock-names = "phyclk";
			clock-output-names = "usb480m_phy3";
			#clock-cells = <0x00>;
			status = "okay";
			phandle = <0x59>;

			host-port {
				#phy-cells = <0x00>;
				status = "okay";
				phandle = <0x5b>;
			};
		};
	};

	syscon@fd5e0000 {
		compatible = "rockchip,rk3588-hdptxphy-grf\0syscon";
		reg = <0x00 0xfd5e0000 0x00 0x100>;
		phandle = <0x160>;
	};

	syscon@fd5e8000 {
		compatible = "rockchip,mipi-dcphy-grf\0syscon";
		reg = <0x00 0xfd5e8000 0x00 0x4000>;
		phandle = <0x164>;
	};

	syscon@fd5ec000 {
		compatible = "rockchip,mipi-dcphy-grf\0syscon";
		reg = <0x00 0xfd5ec000 0x00 0x4000>;
		phandle = <0x165>;
	};

	syscon@fd5f0000 {
		compatible = "rockchip,rk3588-ioc\0syscon";
		reg = <0x00 0xfd5f0000 0x00 0x10000>;
		phandle = <0x169>;
	};

	clock-controller@fd7c0000 {
		compatible = "rockchip,rk3588-cru";
		rockchip,grf = <0x63>;
		reg = <0x00 0xfd7c0000 0x00 0x5c000>;
		#clock-cells = <0x01>;
		#reset-cells = <0x01>;
		assigned-clocks = <0x02 0x09 0x02 0x05 0x02 0x08 0x02 0x07 0x02 0xd8 0x02 0xda 0x02 0xd9 0x02 0x10e 0x02 0x10f 0x02 0x110 0x02 0x299 0x02 0x29a 0x02 0x7b 0x02 0xec 0x02 0x114 0x02 0x208 0x02 0x20e>;
		assigned-clock-rates = <0x4190ab00 0x2ee00000 0x32a9f880 0x46cf7100 0x29d7ab80 0x17d78400 0x1dcd6500 0x2faf0800 0x5f5e100 0x17d78400 0x5f5e100 0xbebc200 0x165a0bc0 0x8f0d180 0xbebc200 0xb71b00 0xb71b00>;
		phandle = <0x02>;
	};

	i2c@fd880000 {
		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
		reg = <0x00 0xfd880000 0x00 0x1000>;
		clocks = <0x02 0x287 0x02 0x286>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x13d 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x64>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";

		rk8602@42 {
			compatible = "rockchip,rk8602";
			reg = <0x42>;
			vin-supply = <0x65>;
			regulator-compatible = "rk860x-reg";
			regulator-name = "vdd_cpu_big0_s0";
			regulator-min-microvolt = <0x86470>;
			regulator-max-microvolt = <0x100590>;
			regulator-ramp-delay = <0x8fc>;
			rockchip,suspend-voltage-selector = <0x01>;
			regulator-boot-on;
			regulator-always-on;
			phandle = <0x12>;

			regulator-state-mem {
				regulator-off-in-suspend;
			};
		};

		rk8603@43 {
			compatible = "rockchip,rk8603";
			reg = <0x43>;
			vin-supply = <0x65>;
			regulator-compatible = "rk860x-reg";
			regulator-name = "vdd_cpu_big1_s0";
			regulator-min-microvolt = <0x86470>;
			regulator-max-microvolt = <0x100590>;
			regulator-ramp-delay = <0x8fc>;
			rockchip,suspend-voltage-selector = <0x01>;
			regulator-boot-on;
			regulator-always-on;
			phandle = <0x16>;

			regulator-state-mem {
				regulator-off-in-suspend;
			};
		};
	};

	serial@fd890000 {
		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfd890000 0x00 0x100>;
		interrupts = <0x00 0x14b 0x04>;
		clocks = <0x02 0x2ae 0x02 0x2af>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0x66 0x06 0x66 0x07>;
		pinctrl-names = "default";
		pinctrl-0 = <0x67>;
		status = "disabled";
	};

	pwm@fd8b0000 {
		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfd8b0000 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x68>;
		clocks = <0x02 0x2a5 0x02 0x2a4>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@fd8b0010 {
		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfd8b0010 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x69>;
		clocks = <0x02 0x2a5 0x02 0x2a4>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@fd8b0020 {
		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfd8b0020 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x6a>;
		clocks = <0x02 0x2a5 0x02 0x2a4>;
		clock-names = "pwm\0pclk";
		status = "okay";
		phandle = <0x184>;
	};

	pwm@fd8b0030 {
		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfd8b0030 0x00 0x10>;
		interrupts = <0x00 0x158 0x04 0x00 0x159 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x6b>;
		clocks = <0x02 0x2a5 0x02 0x2a4>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	power-management@fd8d8000 {
		compatible = "rockchip,rk3588-pmu\0syscon\0simple-mfd";
		reg = <0x00 0xfd8d8000 0x00 0x400>;
		phandle = <0xbf>;

		power-controller {
			compatible = "rockchip,rk3588-power-controller";
			#power-domain-cells = <0x01>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "okay";
			phandle = <0x4f>;

			power-domain@8 {
				reg = <0x08>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				power-domain@9 {
					reg = <0x09>;
					#address-cells = <0x01>;
					#size-cells = <0x00>;
					clocks = <0x02 0x12f 0x02 0x131 0x02 0x130 0x02 0x126>;
					pm_qos = <0x6c 0x6d 0x6e>;

					power-domain@10 {
						reg = <0x0a>;
						clocks = <0x02 0x12f 0x02 0x131 0x02 0x130>;
						pm_qos = <0x6f>;
					};

					power-domain@11 {
						reg = <0x0b>;
						clocks = <0x02 0x12f 0x02 0x131 0x02 0x130>;
						pm_qos = <0x70>;
					};
				};
			};

			power-domain@12 {
				reg = <0x0c>;
				clocks = <0x02 0x114 0x02 0x115 0x02 0x116>;
				pm_qos = <0x71 0x72 0x73 0x74>;
			};

			power-domain@13 {
				reg = <0x0d>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				power-domain@14 {
					reg = <0x0e>;
					clocks = <0x02 0x18f 0x02 0x1be 0x02 0x1bc 0x02 0x190 0x02 0x18e>;
					pm_qos = <0x75>;
				};

				power-domain@15 {
					reg = <0x0f>;
					clocks = <0x02 0x194 0x02 0x1be 0x02 0x1bc 0x02 0x195>;
					pm_qos = <0x76>;
				};

				power-domain@16 {
					reg = <0x10>;
					#address-cells = <0x01>;
					#size-cells = <0x00>;
					clocks = <0x02 0x1c4 0x02 0x1c5>;
					pm_qos = <0x77 0x78 0x79>;

					power-domain@17 {
						reg = <0x11>;
						clocks = <0x02 0x1c9 0x02 0x1c4 0x02 0x1c5 0x02 0x1ca>;
						pm_qos = <0x7a 0x7b 0x7c>;
					};
				};
			};

			power-domain@21 {
				reg = <0x15>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				clocks = <0x02 0x1be 0x02 0x1bd 0x02 0x1bc 0x02 0x1bf 0x02 0x1aa 0x02 0x1a9 0x02 0x1ac 0x02 0x1ad 0x02 0x1ae 0x02 0x1af 0x02 0x1b0 0x02 0x1b1 0x02 0x1b2 0x02 0x1b3 0x02 0x1b4 0x02 0x1b5 0x02 0x1b7 0x02 0x1b6>;
				pm_qos = <0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84>;

				power-domain@23 {
					reg = <0x17>;
					clocks = <0x02 0x4b 0x02 0x49 0x02 0x1be>;
					pm_qos = <0x85>;
				};

				power-domain@14 {
					reg = <0x0e>;
					clocks = <0x02 0x18f 0x02 0x1be 0x02 0x1bc 0x02 0x190>;
					pm_qos = <0x75>;
				};

				power-domain@15 {
					reg = <0x0f>;
					clocks = <0x02 0x194 0x02 0x1be 0x02 0x1bc>;
					pm_qos = <0x76>;
				};

				power-domain@22 {
					reg = <0x16>;
					clocks = <0x02 0x1ba 0x02 0x1b9>;
					pm_qos = <0x86>;
				};
			};

			power-domain@24 {
				reg = <0x18>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				clocks = <0x02 0x26e 0x02 0x26d 0x02 0x270>;
				pm_qos = <0x87 0x88>;

				power-domain@25 {
					reg = <0x19>;
					clocks = <0x02 0x1f6 0x02 0x1f7 0x02 0x1f5 0x02 0x1f3 0x02 0x1ee 0x02 0x1ed 0x02 0x26d>;
					pm_qos = <0x89>;
				};
			};

			power-domain@26 {
				reg = <0x1a>;
				clocks = <0x02 0x22e 0x02 0x22f 0x02 0x22d 0x02 0x218 0x02 0x217 0x02 0x22b 0x02 0x264>;
				pm_qos = <0x8a 0x8b>;
			};

			power-domain@27 {
				reg = <0x1b>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				clocks = <0x02 0x1e1 0x02 0x1e2 0x02 0x1df 0x02 0x1de 0x02 0x1e5 0x02 0x1e4>;
				pm_qos = <0x8c 0x8d 0x8e 0x8f>;

				power-domain@28 {
					reg = <0x1c>;
					clocks = <0x02 0x121 0x02 0x120 0x02 0x1e1 0x02 0x1e2>;
					pm_qos = <0x90 0x91>;
				};

				power-domain@29 {
					reg = <0x1d>;
					clocks = <0x02 0x1d6 0x02 0x1d5 0x02 0x1d9 0x02 0x1d8 0x02 0x1e2>;
					pm_qos = <0x92 0x93>;
				};
			};

			power-domain@30 {
				reg = <0x1e>;
				clocks = <0x02 0x189 0x02 0x18a>;
				pm_qos = <0x94>;
			};

			power-domain@31 {
				reg = <0x1f>;
				clocks = <0x02 0x166 0x02 0x19b 0x02 0x19c 0x02 0x19d 0x02 0x19e 0x02 0x19f 0x02 0x1a0>;
				pm_qos = <0x95 0x96 0x97 0x98>;
			};

			power-domain@33 {
				reg = <0x21>;
				clocks = <0x02 0x166 0x02 0x169 0x02 0x16a>;
			};

			power-domain@34 {
				reg = <0x22>;
				clocks = <0x02 0x166 0x02 0x169 0x02 0x16a>;
			};

			power-domain@37 {
				reg = <0x25>;
				clocks = <0x02 0x199 0x02 0x140>;
				pm_qos = <0x99>;
			};

			power-domain@38 {
				reg = <0x26>;
				clocks = <0x02 0x3c 0x02 0x3d>;
			};

			power-domain@40 {
				reg = <0x28>;
				pm_qos = <0x9a>;
			};
		};
	};

	pvtm@fda40000 {
		compatible = "rockchip,rk3588-bigcore0-pvtm";
		reg = <0x00 0xfda40000 0x00 0x100>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		pvtm@0 {
			reg = <0x00>;
			clocks = <0x02 0x2c6 0x02 0x15>;
			clock-names = "clk\0pclk";
		};
	};

	pvtm@fda50000 {
		compatible = "rockchip,rk3588-bigcore1-pvtm";
		reg = <0x00 0xfda50000 0x00 0x100>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		pvtm@1 {
			reg = <0x01>;
			clocks = <0x02 0x2c8 0x02 0x17>;
			clock-names = "clk\0pclk";
		};
	};

	pvtm@fda60000 {
		compatible = "rockchip,rk3588-litcore-pvtm";
		reg = <0x00 0xfda60000 0x00 0x100>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		pvtm@2 {
			reg = <0x02>;
			clocks = <0x02 0x2ca 0x02 0x1b>;
			clock-names = "clk\0pclk";
		};
	};

	pvtm@fdaf0000 {
		compatible = "rockchip,rk3588-npu-pvtm";
		reg = <0x00 0xfdaf0000 0x00 0x100>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		pvtm@3 {
			reg = <0x03>;
			clocks = <0x02 0x12b 0x02 0x129>;
			clock-names = "clk\0pclk";
			resets = <0x02 0x1de 0x02 0x1dc>;
			reset-names = "rts\0rst-p";
		};
	};

	pvtm@fdb30000 {
		compatible = "rockchip,rk3588-gpu-pvtm";
		reg = <0x00 0xfdb30000 0x00 0x100>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		pvtm@4 {
			reg = <0x04>;
			clocks = <0x02 0x118>;
			clock-names = "clk";
			resets = <0x02 0x430 0x02 0x42f>;
			reset-names = "rts\0rst-p";
		};
	};

	npu@fdab0000 {
		compatible = "rockchip,rk3588-rknpu";
		reg = <0x00 0xfdab0000 0x00 0x10000 0x00 0xfdac0000 0x00 0x10000 0x00 0xfdad0000 0x00 0x10000>;
		interrupts = <0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04>;
		interrupt-names = "npu0_irq\0npu1_irq\0npu2_irq";
		clocks = <0x0e 0x06 0x02 0x12d 0x02 0x122 0x02 0x124 0x02 0x12e 0x02 0x123 0x02 0x125 0x02 0x131>;
		clock-names = "clk_npu\0aclk0\0aclk1\0aclk2\0hclk0\0hclk1\0hclk2\0pclk";
		assigned-clocks = <0x0e 0x06>;
		assigned-clock-rates = <0xbebc200>;
		resets = <0x02 0x1e6 0x02 0x1b0 0x02 0x1c0 0x02 0x1e8 0x02 0x1b2 0x02 0x1c2>;
		reset-names = "srst_a0\0srst_a1\0srst_a2\0srst_h0\0srst_h1\0srst_h2";
		power-domains = <0x4f 0x09 0x4f 0x0a 0x4f 0x0b>;
		power-domain-names = "npu0\0npu1\0npu2";
		operating-points-v2 = <0x9b>;
		iommus = <0x9c>;
		status = "okay";
		rknpu-supply = <0x9d>;
		mem-supply = <0x9d>;
	};

	npu-opp-table {
		compatible = "operating-points-v2";
		nvmem-cells = <0x9e 0x20>;
		nvmem-cell-names = "leakage\0specification_serial_number";
		rockchip,supported-hw;
		rockchip,pvtm-voltage-sel = <0x00 0x32f 0x00 0x330 0x343 0x01 0x344 0x35c 0x02 0x35d 0x375 0x03 0x376 0x38e 0x04 0x38f 0x270f 0x05>;
		rockchip,pvtm-pvtpll;
		rockchip,pvtm-offset = <0x50>;
		rockchip,pvtm-sample-time = <0x44c>;
		rockchip,pvtm-freq = "\0\f5";
		rockchip,pvtm-volt = <0xb71b0>;
		rockchip,pvtm-ref-temp = <0x19>;
		rockchip,pvtm-temp-prop = <0xffffff8f 0xffffff8f>;
		rockchip,pvtm-thermal-zone = "npu-thermal";
		clocks = <0x02 0x12a>;
		clock-names = "pclk";
		rockchip,grf = <0x9f>;
		volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>;
		low-volt-read-margin = <0x04>;
		intermediate-threshold-freq = <0x7a120>;
		rockchip,init-freq = <0xf4240>;
		rockchip,temp-hysteresis = <0x1388>;
		rockchip,low-temp = <0x2710>;
		rockchip,low-temp-min-volt = <0xb71b0>;
		rockchip,high-temp = <0x14c08>;
		rockchip,high-temp-max-freq = "\0\f5";
		phandle = <0x9b>;

		opp-300000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x11e1a300>;
			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
			opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
		};

		opp-400000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x17d78400>;
			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
			opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
		};

		opp-500000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x1dcd6500>;
			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
			opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
		};

		opp-600000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
			opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
		};

		opp-700000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x29b92700>;
			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
			opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
		};

		opp-800000000 {
			opp-supported-hw = <0xff 0xffff>;
			opp-hz = <0x00 0x2faf0800>;
			opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
			opp-microvolt-L2 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>;
			opp-microvolt-L3 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>;
			opp-microvolt-L4 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>;
			opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
		};

		opp-900000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x35a4e900>;
			opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
			opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
			opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>;
			opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>;
			opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
			opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>;
		};

		opp-1000000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x3b9aca00>;
			opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>;
			opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>;
			opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>;
			opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>;
			opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
			opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
		};
	};

	iommu@fdab9000 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdab9000 0x00 0x100 0x00 0xfdaba000 0x00 0x100 0x00 0xfdaca000 0x00 0x100 0x00 0xfdada000 0x00 0x100>;
		interrupts = <0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04>;
		interrupt-names = "npu0_mmu\0npu1_mmu\0npu2_mmu";
		clocks = <0x02 0x12d 0x02 0x122 0x02 0x124 0x02 0x12e 0x02 0x123 0x02 0x125>;
		clock-names = "aclk0\0aclk1\0aclk2\0iface0\0iface1\0iface2";
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0x9c>;
	};

	vepu@fdb50000 {
		compatible = "rockchip,vpu-encoder-v2";
		reg = <0x00 0xfdb50000 0x00 0x400>;
		interrupts = <0x00 0x78 0x04>;
		interrupt-names = "irq_vepu";
		clocks = <0x02 0x1c0 0x02 0x1c1>;
		clock-names = "aclk_vcodec\0hclk_vcodec";
		rockchip,normal-rates = <0x2367b880 0x00>;
		assigned-clocks = <0x02 0x1c0>;
		assigned-clock-rates = <0x2367b880>;
		resets = <0x02 0x2c8 0x02 0x2c9>;
		reset-names = "shared_video_a\0shared_video_h";
		rockchip,skip-pmu-idle-request;
		iommus = <0xa0>;
		rockchip,srv = <0xa1>;
		rockchip,taskqueue-node = <0x00>;
		rockchip,resetgroup-node = <0x00>;
		power-domains = <0x4f 0x15>;
		status = "disabled";
	};

	vdpu@fdb50400 {
		compatible = "rockchip,vpu-decoder-v2";
		reg = <0x00 0xfdb50400 0x00 0x400>;
		interrupts = <0x00 0x77 0x04>;
		interrupt-names = "irq_vdpu";
		clocks = <0x02 0x1c0 0x02 0x1c1>;
		clock-names = "aclk_vcodec\0hclk_vcodec";
		rockchip,normal-rates = <0x2367b880 0x00>;
		assigned-clocks = <0x02 0x1c0>;
		assigned-clock-rates = <0x2367b880>;
		resets = <0x02 0x2c8 0x02 0x2c9>;
		reset-names = "shared_video_a\0shared_video_h";
		rockchip,skip-pmu-idle-request;
		iommus = <0xa0>;
		rockchip,srv = <0xa1>;
		rockchip,taskqueue-node = <0x00>;
		rockchip,resetgroup-node = <0x00>;
		power-domains = <0x4f 0x15>;
		status = "okay";
	};

	iommu@fdb50800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdb50800 0x00 0x40>;
		interrupts = <0x00 0x76 0x04>;
		interrupt-names = "irq_vdpu_mmu";
		clocks = <0x02 0x1c0 0x02 0x1c1>;
		clock-names = "aclk\0iface";
		power-domains = <0x4f 0x15>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0xa0>;
	};

	avsd-plus@fdb51000 {
		compatible = "rockchip,avs-plus-decoder";
		reg = <0x00 0xfdb51000 0x00 0x200>;
		interrupts = <0x00 0x77 0x04>;
		interrupt-names = "irq_avsd";
		clocks = <0x02 0x1c0 0x02 0x1c1>;
		clock-names = "aclk_vcodec\0hclk_vcodec";
		resets = <0x02 0x2c8 0x02 0x2c9>;
		reset-names = "shared_video_a\0shared_video_h";
		rockchip,skip-pmu-idle-request;
		iommus = <0xa0>;
		power-domains = <0x4f 0x15>;
		rockchip,srv = <0xa1>;
		rockchip,taskqueue-node = <0x00>;
		rockchip,resetgroup-node = <0x00>;
		status = "disabled";
	};

	rga@fdb60000 {
		compatible = "rockchip,rga3_core0";
		reg = <0x00 0xfdb60000 0x00 0x1000>;
		interrupts = <0x00 0x72 0x04>;
		interrupt-names = "rga3_core0_irq";
		clocks = <0x02 0x1ba 0x02 0x1b9 0x02 0x1bb>;
		clock-names = "aclk_rga3_0\0hclk_rga3_0\0clk_rga3_0";
		power-domains = <0x4f 0x16>;
		iommus = <0xa2>;
		status = "okay";
	};

	iommu@fdb60f00 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdb60f00 0x00 0x100>;
		interrupts = <0x00 0x72 0x04>;
		interrupt-names = "rga3_0_mmu";
		clocks = <0x02 0x1ba 0x02 0x1b9>;
		clock-names = "aclk\0iface";
		power-domains = <0x4f 0x16>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0xa2>;
	};

	rga@fdb70000 {
		compatible = "rockchip,rga3_core1";
		reg = <0x00 0xfdb70000 0x00 0x1000>;
		interrupts = <0x00 0x73 0x04>;
		interrupt-names = "rga3_core1_irq";
		clocks = <0x02 0x18a 0x02 0x189 0x02 0x18b>;
		clock-names = "aclk_rga3_1\0hclk_rga3_1\0clk_rga3_1";
		power-domains = <0x4f 0x1e>;
		iommus = <0xa3>;
		status = "okay";
	};

	iommu@fdb70f00 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdb70f00 0x00 0x100>;
		interrupts = <0x00 0x73 0x04>;
		interrupt-names = "rga3_1_mmu";
		clocks = <0x02 0x18a 0x02 0x189>;
		clock-names = "aclk\0iface";
		power-domains = <0x4f 0x1e>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0xa3>;
	};

	rga@fdb80000 {
		compatible = "rockchip,rga2_core0";
		reg = <0x00 0xfdb80000 0x00 0x1000>;
		interrupts = <0x00 0x74 0x04>;
		interrupt-names = "rga2_irq";
		clocks = <0x02 0x1b7 0x02 0x1b6 0x02 0x1b8>;
		clock-names = "aclk_rga2\0hclk_rga2\0clk_rga2";
		power-domains = <0x4f 0x15>;
		status = "okay";
	};

	jpegd@fdb90000 {
		compatible = "rockchip,rkv-jpeg-decoder-v1";
		reg = <0x00 0xfdb90000 0x00 0x400>;
		interrupts = <0x00 0x81 0x04>;
		interrupt-names = "irq_jpegd";
		clocks = <0x02 0x1b4 0x02 0x1b5>;
		clock-names = "aclk_vcodec\0hclk_vcodec";
		rockchip,normal-rates = <0x23c34600 0x00>;
		assigned-clocks = <0x02 0x1b4>;
		assigned-clock-rates = <0x23c34600>;
		resets = <0x02 0x2d2 0x02 0x2d3>;
		reset-names = "video_a\0video_h";
		rockchip,skip-pmu-idle-request;
		iommus = <0xa4>;
		rockchip,srv = <0xa1>;
		rockchip,taskqueue-node = <0x01>;
		power-domains = <0x4f 0x15>;
		status = "okay";
	};

	iommu@fdb90480 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdb90480 0x00 0x40>;
		interrupts = <0x00 0x82 0x04>;
		interrupt-names = "irq_jpegd_mmu";
		clocks = <0x02 0x1b4 0x02 0x1b5>;
		clock-names = "aclk\0iface";
		power-domains = <0x4f 0x15>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0xa4>;
	};

	jpege-core@fdba0000 {
		compatible = "rockchip,vpu-jpege-core";
		reg = <0x00 0xfdba0000 0x00 0x400>;
		interrupts = <0x00 0x7a 0x04>;
		interrupt-names = "irq_jpege0";
		clocks = <0x02 0x1ac 0x02 0x1ad>;
		clock-names = "aclk_vcodec\0hclk_vcodec";
		rockchip,normal-rates = <0x2367b880 0x00>;
		assigned-clocks = <0x02 0x1ac>;
		assigned-clock-rates = <0x2367b880>;
		resets = <0x02 0x2ca 0x02 0x2cb>;
		reset-names = "video_a\0video_h";
		rockchip,skip-pmu-idle-request;
		iommus = <0xa5>;
		rockchip,srv = <0xa1>;
		rockchip,taskqueue-node = <0x02>;
		rockchip,ccu = <0xa6>;
		power-domains = <0x4f 0x15>;
		status = "okay";
	};

	iommu@fdba0800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdba0800 0x00 0x40>;
		interrupts = <0x00 0x79 0x04>;
		interrupt-names = "irq_jpege0_mmu";
		clocks = <0x02 0x1ac 0x02 0x1ad>;
		clock-names = "aclk\0iface";
		power-domains = <0x4f 0x15>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0xa5>;
	};

	jpege-core@fdba4000 {
		compatible = "rockchip,vpu-jpege-core";
		reg = <0x00 0xfdba4000 0x00 0x400>;
		interrupts = <0x00 0x7c 0x04>;
		interrupt-names = "irq_jpege1";
		clocks = <0x02 0x1ae 0x02 0x1af>;
		clock-names = "aclk_vcodec\0hclk_vcodec";
		rockchip,normal-rates = <0x2367b880 0x00>;
		assigned-clocks = <0x02 0x1ae>;
		assigned-clock-rates = <0x2367b880>;
		resets = <0x02 0x2cc 0x02 0x2cd>;
		reset-names = "video_a\0video_h";
		rockchip,skip-pmu-idle-request;
		iommus = <0xa7>;
		rockchip,srv = <0xa1>;
		rockchip,taskqueue-node = <0x02>;
		rockchip,ccu = <0xa6>;
		power-domains = <0x4f 0x15>;
		status = "okay";
	};

	iommu@fdba4800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdba4800 0x00 0x40>;
		interrupts = <0x00 0x7b 0x04>;
		interrupt-names = "irq_jpege1_mmu";
		clocks = <0x02 0x1ae 0x02 0x1af>;
		clock-names = "aclk\0iface";
		power-domains = <0x4f 0x15>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0xa7>;
	};

	jpege-core@fdba8000 {
		compatible = "rockchip,vpu-jpege-core";
		reg = <0x00 0xfdba8000 0x00 0x400>;
		interrupts = <0x00 0x7e 0x04>;
		interrupt-names = "irq_jpege2";
		clocks = <0x02 0x1b0 0x02 0x1b1>;
		clock-names = "aclk_vcodec\0hclk_vcodec";
		rockchip,normal-rates = <0x2367b880 0x00>;
		assigned-clocks = <0x02 0x1b0>;
		assigned-clock-rates = <0x2367b880>;
		resets = <0x02 0x2ce 0x02 0x2cf>;
		reset-names = "video_a\0video_h";
		rockchip,skip-pmu-idle-request;
		iommus = <0xa8>;
		rockchip,srv = <0xa1>;
		rockchip,taskqueue-node = <0x02>;
		rockchip,ccu = <0xa6>;
		power-domains = <0x4f 0x15>;
		status = "okay";
	};

	iommu@fdba8800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdba8800 0x00 0x40>;
		interrupts = <0x00 0x7d 0x04>;
		interrupt-names = "irq_jpege2_mmu";
		clocks = <0x02 0x1b0 0x02 0x1b1>;
		clock-names = "aclk\0iface";
		power-domains = <0x4f 0x15>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0xa8>;
	};

	jpege-core@fdbac000 {
		compatible = "rockchip,vpu-jpege-core";
		reg = <0x00 0xfdbac000 0x00 0x400>;
		interrupts = <0x00 0x80 0x04>;
		interrupt-names = "irq_jpege3";
		clocks = <0x02 0x1b2 0x02 0x1b3>;
		clock-names = "aclk_vcodec\0hclk_vcodec";
		rockchip,normal-rates = <0x2367b880 0x00>;
		assigned-clocks = <0x02 0x1b2>;
		assigned-clock-rates = <0x2367b880>;
		resets = <0x02 0x2d0 0x02 0x2d1>;
		reset-names = "video_a\0video_h";
		rockchip,skip-pmu-idle-request;
		iommus = <0xa9>;
		rockchip,srv = <0xa1>;
		rockchip,taskqueue-node = <0x02>;
		rockchip,ccu = <0xa6>;
		power-domains = <0x4f 0x15>;
		status = "okay";
	};

	iommu@fdbac800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdbac800 0x00 0x40>;
		interrupts = <0x00 0x7f 0x04>;
		interrupt-names = "irq_jpege3_mmu";
		clocks = <0x02 0x1b2 0x02 0x1b3>;
		clock-names = "aclk\0iface";
		power-domains = <0x4f 0x15>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0xa9>;
	};

	iep@fdbb0000 {
		compatible = "rockchip,iep-v2";
		reg = <0x00 0xfdbb0000 0x00 0x500>;
		interrupts = <0x00 0x75 0x04>;
		interrupt-names = "irq_iep";
		clocks = <0x02 0x1aa 0x02 0x1a9 0x02 0x1ab>;
		clock-names = "aclk\0hclk\0sclk";
		resets = <0x02 0x2d5 0x02 0x2d4 0x02 0x2d6>;
		reset-names = "rst_a\0rst_h\0rst_s";
		rockchip,skip-pmu-idle-request;
		power-domains = <0x4f 0x15>;
		rockchip,srv = <0xa1>;
		rockchip,taskqueue-node = <0x06>;
		iommus = <0xaa>;
		status = "okay";
	};

	iommu@fdbb0800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdbb0800 0x00 0x100>;
		interrupts = <0x00 0x75 0x04>;
		interrupt-names = "irq_iep_mmu";
		clocks = <0x02 0x1aa 0x02 0x1a9>;
		clock-names = "aclk\0iface";
		#iommu-cells = <0x00>;
		power-domains = <0x4f 0x15>;
		status = "okay";
		phandle = <0xaa>;
	};

	rkvenc-core@fdbd0000 {
		compatible = "rockchip,rkv-encoder-v2-core";
		reg = <0x00 0xfdbd0000 0x00 0x6000>;
		interrupts = <0x00 0x65 0x04>;
		interrupt-names = "irq_rkvenc0";
		clocks = <0x02 0x1c5 0x02 0x1c4 0x02 0x1c6>;
		clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core";
		rockchip,normal-rates = <0x23c34600 0x00 0x2faf0800>;
		assigned-clocks = <0x02 0x1c5 0x02 0x1c6>;
		assigned-clock-rates = <0x23c34600 0x2faf0800>;
		resets = <0x02 0x2f5 0x02 0x2f4 0x02 0x2f6>;
		reset-names = "video_a\0video_h\0video_core";
		rockchip,skip-pmu-idle-request;
		iommus = <0xab>;
		rockchip,srv = <0xa1>;
		rockchip,ccu = <0xac>;
		rockchip,taskqueue-node = <0x07>;
		rockchip,task-capacity = <0x08>;
		power-domains = <0x4f 0x10>;
		status = "okay";
	};

	iommu@fdbdf000 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdbdf000 0x00 0x40 0x00 0xfdbdf040 0x00 0x40>;
		interrupts = <0x00 0x63 0x04 0x00 0x64 0x04>;
		interrupt-names = "irq_rkvenc0_mmu0\0irq_rkvenc0_mmu1";
		clocks = <0x02 0x1c5 0x02 0x1c4>;
		clock-names = "aclk\0iface";
		rockchip,disable-mmu-reset;
		rockchip,enable-cmd-retry;
		rockchip,shootdown-entire;
		#iommu-cells = <0x00>;
		power-domains = <0x4f 0x10>;
		status = "okay";
		phandle = <0xab>;
	};

	rkvenc-core@fdbe0000 {
		compatible = "rockchip,rkv-encoder-v2-core";
		reg = <0x00 0xfdbe0000 0x00 0x6000>;
		interrupts = <0x00 0x68 0x04>;
		interrupt-names = "irq_rkvenc1";
		clocks = <0x02 0x1ca 0x02 0x1c9 0x02 0x1cb>;
		clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core";
		rockchip,normal-rates = <0x23c34600 0x00 0x2faf0800>;
		assigned-clocks = <0x02 0x1ca 0x02 0x1cb>;
		assigned-clock-rates = <0x23c34600 0x2faf0800>;
		resets = <0x02 0x305 0x02 0x304 0x02 0x306>;
		reset-names = "video_a\0video_h\0video_core";
		rockchip,skip-pmu-idle-request;
		iommus = <0xad>;
		rockchip,srv = <0xa1>;
		rockchip,ccu = <0xac>;
		rockchip,taskqueue-node = <0x07>;
		rockchip,task-capacity = <0x08>;
		power-domains = <0x4f 0x11>;
		status = "okay";
	};

	iommu@fdbef000 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdbef000 0x00 0x40 0x00 0xfdbef040 0x00 0x40>;
		interrupts = <0x00 0x66 0x04 0x00 0x67 0x04>;
		interrupt-names = "irq_rkvenc1_mmu0\0irq_rkvenc1_mmu1";
		clocks = <0x02 0x1ca 0x02 0x1c9>;
		lock-names = "aclk\0iface";
		rockchip,disable-mmu-reset;
		rockchip,enable-cmd-retry;
		rockchip,shootdown-entire;
		#iommu-cells = <0x00>;
		power-domains = <0x4f 0x11>;
		status = "okay";
		phandle = <0xad>;
	};

	rkvdec-ccu@fdc30000 {
		compatible = "rockchip,rkv-decoder-v2-ccu";
		reg = <0x00 0xfdc30000 0x00 0x100>;
		reg-names = "ccu";
		clocks = <0x02 0x18e>;
		clock-names = "aclk_ccu";
		assigned-clocks = <0x02 0x18e>;
		assigned-clock-rates = <0x23c34600>;
		resets = <0x02 0x282>;
		reset-names = "video_ccu";
		rockchip,skip-pmu-idle-request;
		power-domains = <0x4f 0x0e>;
		status = "okay";
		phandle = <0xaf>;
	};

	rkvdec-core@fdc38000 {
		compatible = "rockchip,rkv-decoder-v2";
		reg = <0x00 0xfdc38100 0x00 0x400 0x00 0xfdc38000 0x00 0x100>;
		reg-names = "regs\0link";
		interrupts = <0x00 0x5f 0x04>;
		interrupt-names = "irq_rkvdec0";
		clocks = <0x02 0x190 0x02 0x18f 0x02 0x193 0x02 0x191 0x02 0x192>;
		clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac";
		rockchip,normal-rates = <0x2faf0800 0x00 0x23c34600 0x23c34600 0x3b9aca00>;
		assigned-clocks = <0x02 0x190 0x02 0x193 0x02 0x191 0x02 0x192>;
		assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>;
		resets = <0x02 0x284 0x02 0x283 0x02 0x289 0x02 0x287 0x02 0x288>;
		reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac";
		rockchip,skip-pmu-idle-request;
		iommus = <0xae>;
		rockchip,srv = <0xa1>;
		rockchip,ccu = <0xaf>;
		rockchip,core-mask = <0x10001>;
		rockchip,taskqueue-node = <0x09>;
		rockchip,sram = <0xb0>;
		rockchip,rcb-iova = <0xfff00000 0x100000>;
		rockchip,rcb-min-width = <0x200>;
		power-domains = <0x4f 0x0e>;
		status = "okay";
	};

	iommu@fdc38700 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdc38700 0x00 0x40 0x00 0xfdc38740 0x00 0x40>;
		interrupts = <0x00 0x60 0x04>;
		interrupt-names = "irq_rkvdec0_mmu";
		clocks = <0x02 0x190 0x02 0x18f>;
		clock-names = "aclk\0iface";
		rockchip,disable-mmu-reset;
		rockchip,enable-cmd-retry;
		rockchip,shootdown-entire;
		rockchip,master-handle-irq;
		#iommu-cells = <0x00>;
		power-domains = <0x4f 0x0e>;
		status = "okay";
		phandle = <0xae>;
	};

	rkvdec-core@fdc48000 {
		compatible = "rockchip,rkv-decoder-v2";
		reg = <0x00 0xfdc48100 0x00 0x400 0x00 0xfdc48000 0x00 0x100>;
		reg-names = "regs\0link";
		interrupts = <0x00 0x61 0x04>;
		interrupt-names = "irq_rkvdec1";
		clocks = <0x02 0x195 0x02 0x194 0x02 0x198 0x02 0x196 0x02 0x197>;
		clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac";
		rockchip,normal-rates = <0x2faf0800 0x00 0x23c34600 0x23c34600 0x3b9aca00>;
		assigned-clocks = <0x02 0x195 0x02 0x198 0x02 0x196 0x02 0x197>;
		assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>;
		resets = <0x02 0x293 0x02 0x292 0x02 0x298 0x02 0x296 0x02 0x297>;
		reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac";
		rockchip,skip-pmu-idle-request;
		iommus = <0xb1>;
		rockchip,srv = <0xa1>;
		rockchip,ccu = <0xaf>;
		rockchip,core-mask = <0x20002>;
		rockchip,taskqueue-node = <0x09>;
		rockchip,sram = <0xb2>;
		rockchip,rcb-iova = <0xffe00000 0x100000>;
		rockchip,rcb-min-width = <0x200>;
		power-domains = <0x4f 0x0f>;
		status = "okay";
	};

	iommu@fdc48700 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdc48700 0x00 0x40 0x00 0xfdc48740 0x00 0x40>;
		interrupts = <0x00 0x62 0x04>;
		interrupt-names = "irq_rkvdec1_mmu";
		clocks = <0x02 0x195 0x02 0x194>;
		clock-names = "aclk\0iface";
		rockchip,disable-mmu-reset;
		rockchip,enable-cmd-retry;
		rockchip,shootdown-entire;
		rockchip,master-handle-irq;
		#iommu-cells = <0x00>;
		power-domains = <0x4f 0x0f>;
		status = "okay";
		phandle = <0xb1>;
	};

	av1d@fdc70000 {
		compatible = "rockchip,av1-decoder";
		reg = <0x00 0xfdc70000 0x00 0x800 0x00 0xfdc80000 0x00 0x400 0x00 0xfdc90000 0x00 0x400>;
		reg-names = "vcd\0cache\0afbc";
		interrupts = <0x00 0x6c 0x04 0x00 0x6b 0x04 0x00 0x6a 0x04>;
		interrupt-names = "irq_av1d\0irq_cache\0irq_afbc";
		clocks = <0x02 0x49 0x02 0x4b>;
		clock-names = "aclk_vcodec\0hclk_vcodec";
		rockchip,normal-rates = <0x17d78400 0x17d78400>;
		assigned-clocks = <0x02 0x49 0x02 0x4b>;
		assigned-clock-rates = <0x17d78400 0x17d78400>;
		resets = <0x02 0x442 0x02 0x445>;
		reset-names = "video_a\0video_h";
		iommus = <0xb3>;
		rockchip,srv = <0xa1>;
		rockchip,taskqueue-node = <0x0b>;
		power-domains = <0x4f 0x17>;
		status = "disabled";
	};

	iommu@fdca0000 {
		compatible = "rockchip,iommu-av1";
		reg = <0x00 0xfdca0000 0x00 0x600>;
		interrupts = <0x00 0x6d 0x04>;
		interrupt-names = "irq_av1d_mmu";
		clocks = <0x02 0x49 0x02 0x4b>;
		clock-names = "aclk\0iface";
		#iommu-cells = <0x00>;
		power-domains = <0x4f 0x17>;
		status = "disabled";
		phandle = <0xb3>;
	};

	rkisp-unite@fdcb0000 {
		compatible = "rockchip,rk3588-rkisp-unite";
		reg = <0x00 0xfdcb0000 0x00 0x10000 0x00 0xfdcc0000 0x00 0x10000>;
		interrupts = <0x00 0x87 0x04 0x00 0x89 0x04 0x00 0x8a 0x04>;
		interrupt-names = "isp_irq\0mi_irq\0mipi_irq";
		clocks = <0x02 0x1de 0x02 0x1df 0x02 0x1db 0x02 0x1dc 0x02 0x1dd 0x02 0x120 0x02 0x121 0x02 0x11d 0x02 0x11e 0x02 0x11f>;
		clock-names = "aclk_isp0\0hclk_isp0\0clk_isp_core0\0clk_isp_core_marvin0\0clk_isp_core_vicap0\0aclk_isp1\0hclk_isp1\0clk_isp_core1\0clk_isp_core_marvin1\0clk_isp_core_vicap1";
		power-domains = <0x4f 0x1c>;
		iommus = <0xb4>;
		status = "disabled";
	};

	rkisp@fdcb0000 {
		compatible = "rockchip,rk3588-rkisp";
		reg = <0x00 0xfdcb0000 0x00 0x7f00>;
		interrupts = <0x00 0x83 0x04 0x00 0x85 0x04 0x00 0x86 0x04>;
		interrupt-names = "isp_irq\0mi_irq\0mipi_irq";
		clocks = <0x02 0x1de 0x02 0x1df 0x02 0x1db 0x02 0x1dc 0x02 0x1dd>;
		clock-names = "aclk_isp\0hclk_isp\0clk_isp_core\0clk_isp_core_marvin\0clk_isp_core_vicap";
		power-domains = <0x4f 0x1b>;
		iommus = <0xb5>;
		status = "okay";
		phandle = <0x47>;
	};

	rkisp-unite-mmu@fdcb7f00 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdcb7f00 0x00 0x100 0x00 0xfdcc7f00 0x00 0x100>;
		interrupts = <0x00 0x84 0x04 0x00 0x88 0x04>;
		interrupt-names = "isp0_mmu\0isp1_mmu";
		clocks = <0x02 0x1de 0x02 0x1df 0x02 0x120 0x02 0x121>;
		clock-names = "aclk0\0iface0\0aclk1\0iface1";
		power-domains = <0x4f 0x1c>;
		#iommu-cells = <0x00>;
		rockchip,disable-mmu-reset;
		status = "disabled";
		phandle = <0xb4>;
	};

	iommu@fdcb7f00 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdcb7f00 0x00 0x100>;
		interrupts = <0x00 0x84 0x04>;
		interrupt-names = "isp0_mmu";
		clocks = <0x02 0x1de 0x02 0x1df>;
		clock-names = "aclk\0iface";
		power-domains = <0x4f 0x1b>;
		#iommu-cells = <0x00>;
		rockchip,disable-mmu-reset;
		status = "okay";
		phandle = <0xb5>;
	};

	rkisp@fdcc0000 {
		compatible = "rockchip,rk3588-rkisp";
		reg = <0x00 0xfdcc0000 0x00 0x7f00>;
		interrupts = <0x00 0x87 0x04 0x00 0x89 0x04 0x00 0x8a 0x04>;
		interrupt-names = "isp_irq\0mi_irq\0mipi_irq";
		clocks = <0x02 0x120 0x02 0x121 0x02 0x11d 0x02 0x11e 0x02 0x11f>;
		clock-names = "aclk_isp\0hclk_isp\0clk_isp_core\0clk_isp_core_marvin\0clk_isp_core_vicap";
		power-domains = <0x4f 0x1c>;
		iommus = <0xb6>;
		status = "disabled";
		phandle = <0x49>;
	};

	iommu@fdcc7f00 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdcc7f00 0x00 0x100>;
		interrupts = <0x00 0x88 0x04>;
		interrupt-names = "isp1_mmu";
		clocks = <0x02 0x120 0x02 0x121>;
		clock-names = "aclk\0iface";
		power-domains = <0x4f 0x1c>;
		#iommu-cells = <0x00>;
		rockchip,disable-mmu-reset;
		status = "disabled";
		phandle = <0xb6>;
	};

	rkispp@fdcd0000 {
		compatible = "rockchip,rk3588-rkispp";
		reg = <0x00 0xfdcd0000 0x00 0xf00>;
		interrupts = <0x00 0x8b 0x04>;
		interrupt-names = "fec_irq";
		clocks = <0x02 0x1d5 0x02 0x1d6 0x02 0x1d7>;
		clock-names = "aclk_ispp\0hclk_ispp\0clk_ispp";
		assigned-clocks = <0x02 0x1d6>;
		assigned-clock-rates = <0x5f5e100>;
		power-domains = <0x4f 0x1d>;
		iommus = <0xb7>;
		status = "disabled";
		phandle = <0x4a>;
	};

	iommu@fdcd0f00 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdcd0f00 0x00 0x100>;
		interrupts = <0x00 0x8c 0x04>;
		interrupt-names = "fec0_mmu";
		clocks = <0x02 0x1d5 0x02 0x1d6 0x02 0x1d7>;
		clock-names = "aclk\0iface\0pclk";
		power-domains = <0x4f 0x1d>;
		#iommu-cells = <0x00>;
		rockchip,disable-mmu-reset;
		status = "disabled";
		phandle = <0xb7>;
	};

	rkispp@fdcd8000 {
		compatible = "rockchip,rk3588-rkispp";
		reg = <0x00 0xfdcd8000 0x00 0xf00>;
		interrupts = <0x00 0x8d 0x04>;
		interrupt-names = "fec_irq";
		clocks = <0x02 0x1d8 0x02 0x1d9 0x02 0x1da>;
		clock-names = "aclk_ispp\0hclk_ispp\0clk_ispp";
		assigned-clocks = <0x02 0x1d9>;
		assigned-clock-rates = <0x5f5e100>;
		power-domains = <0x4f 0x1d>;
		iommus = <0xb8>;
		status = "disabled";
		phandle = <0x4b>;
	};

	iommu@fdcd8f00 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdcd8f00 0x00 0x100>;
		interrupts = <0x00 0x8e 0x04>;
		interrupt-names = "fec1_mmu";
		clocks = <0x02 0x1d8 0x02 0x1d9 0x02 0x1da>;
		clock-names = "aclk\0iface\0pclk";
		power-domains = <0x4f 0x1d>;
		#iommu-cells = <0x00>;
		rockchip,disable-mmu-reset;
		status = "disabled";
		phandle = <0xb8>;
	};

	rkcif@fdce0000 {
		compatible = "rockchip,rk3588-cif";
		reg = <0x00 0xfdce0000 0x00 0x800>;
		reg-names = "cif_regs";
		interrupts = <0x00 0x9b 0x04>;
		interrupt-names = "cif-intr";
		clocks = <0x02 0x1e4 0x02 0x1e5 0x02 0x1e3>;
		clock-names = "aclk_cif\0hclk_cif\0dclk_cif";
		resets = <0x02 0x317 0x02 0x318 0x02 0x316>;
		reset-names = "rst_cif_a\0rst_cif_h\0rst_cif_d";
		assigned-clocks = <0x02 0x1e3>;
		assigned-clock-rates = <0x23c34600>;
		power-domains = <0x4f 0x1b>;
		rockchip,grf = <0xb9>;
		iommus = <0x3f>;
		status = "okay";
		phandle = <0x3e>;
	};

	iommu@fdce0800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdce0800 0x00 0x100 0x00 0xfdce0900 0x00 0x100>;
		interrupts = <0x00 0x71 0x04>;
		interrupt-names = "cif_mmu";
		clocks = <0x02 0x1e4 0x02 0x1e5>;
		clock-names = "aclk\0iface";
		power-domains = <0x4f 0x1b>;
		rockchip,disable-mmu-reset;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0x3f>;
	};

	mipi0-csi2@fdd10000 {
		compatible = "rockchip,rk3588-mipi-csi2";
		reg = <0x00 0xfdd10000 0x00 0x10000>;
		reg-names = "csihost_regs";
		interrupts = <0x00 0x8f 0x04 0x00 0x90 0x04>;
		interrupt-names = "csi-intr1\0csi-intr2";
		clocks = <0x02 0x1cf 0x02 0x1cd>;
		clock-names = "pclk_csi2host\0iclk_csi2host";
		resets = <0x02 0x324 0x02 0x334>;
		reset-names = "srst_csihost_p\0srst_csihost_vicap";
		status = "disabled";
	};

	mipi1-csi2@fdd20000 {
		compatible = "rockchip,rk3588-mipi-csi2";
		reg = <0x00 0xfdd20000 0x00 0x10000>;
		reg-names = "csihost_regs";
		interrupts = <0x00 0x91 0x04 0x00 0x92 0x04>;
		interrupt-names = "csi-intr1\0csi-intr2";
		clocks = <0x02 0x1d0 0x02 0x1ce>;
		clock-names = "pclk_csi2host\0iclk_csi2host";
		resets = <0x02 0x325 0x02 0x335>;
		reset-names = "srst_csihost_p\0srst_csihost_vicap";
		status = "disabled";
	};

	mipi2-csi2@fdd30000 {
		compatible = "rockchip,rk3588-mipi-csi2";
		reg = <0x00 0xfdd30000 0x00 0x10000>;
		reg-names = "csihost_regs";
		interrupts = <0x00 0x93 0x04 0x00 0x94 0x04>;
		interrupt-names = "csi-intr1\0csi-intr2";
		clocks = <0x02 0x1d1>;
		clock-names = "pclk_csi2host";
		resets = <0x02 0x326 0x02 0x336>;
		reset-names = "srst_csihost_p\0srst_csihost_vicap";
		status = "okay";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xba>;
					phandle = <0x30>;
				};
			};

			port@1 {
				reg = <0x01>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xbb>;
					phandle = <0x43>;
				};
			};
		};
	};

	mipi3-csi2@fdd40000 {
		compatible = "rockchip,rk3588-mipi-csi2";
		reg = <0x00 0xfdd40000 0x00 0x10000>;
		reg-names = "csihost_regs";
		interrupts = <0x00 0x95 0x04 0x00 0x96 0x04>;
		interrupt-names = "csi-intr1\0csi-intr2";
		clocks = <0x02 0x1d2>;
		clock-names = "pclk_csi2host";
		resets = <0x02 0x327 0x02 0x337>;
		reset-names = "srst_csihost_p\0srst_csihost_vicap";
		status = "disabled";
	};

	vop@fdd90000 {
		compatible = "rockchip,rk3588-vop";
		reg = <0x00 0xfdd90000 0x00 0x4200 0x00 0xfdd95000 0x00 0x1000>;
		reg-names = "regs\0gamma_lut";
		interrupts = <0x00 0x9c 0x04>;
		clocks = <0x02 0x270 0x02 0x26f 0x02 0x274 0x02 0x275 0x02 0x276 0x02 0x277 0x02 0x26e 0x02 0x271 0x02 0x272 0x02 0x273>;
		clock-names = "aclk_vop\0hclk_vop\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0pclk_vop\0dclk_src_vp0\0dclk_src_vp1\0dclk_src_vp2";
		assigned-clocks = <0x02 0x270>;
		assigned-clock-rates = <0x2faf0800>;
		resets = <0x02 0x349 0x02 0x348 0x02 0x34d 0x02 0x350 0x02 0x351 0x02 0x352>;
		reset-names = "axi\0ahb\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3";
		iommus = <0xbc>;
		power-domains = <0x4f 0x18>;
		rockchip,grf = <0xb9>;
		rockchip,vop-grf = <0xbd>;
		rockchip,vo1-grf = <0xbe>;
		rockchip,pmu = <0xbf>;
		status = "okay";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			phandle = <0x31>;

			port@0 {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				reg = <0x00>;
				assigned-clocks = <0x02 0x274>;
				assigned-clock-parents = <0x32>;
				cursor-win-id = <0x00>;
				rockchip,plane-mask = <0x05>;
				rockchip,primary-plane = <0x02>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xc0>;
					phandle = <0xd9>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xc1>;
					phandle = <0xe4>;
				};

				endpoint@2 {
					reg = <0x02>;
					remote-endpoint = <0xc2>;
					phandle = <0x38>;
				};
			};

			port@1 {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				reg = <0x01>;
				cursor-win-id = <0x01>;
				rockchip,plane-mask = <0x0a>;
				rockchip,primary-plane = <0x03>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xc3>;
					phandle = <0x34>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xc4>;
					phandle = <0xe5>;
				};

				endpoint@2 {
					reg = <0x02>;
					remote-endpoint = <0xc5>;
					phandle = <0xe1>;
				};
			};

			port@2 {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				reg = <0x02>;
				assigned-clocks = <0x02 0x273>;
				assigned-clock-parents = <0x02 0x04>;
				cursor-win-id = <0x06>;
				rockchip,plane-mask = <0x140>;
				rockchip,primary-plane = <0x08>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xc6>;
					phandle = <0xda>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xc7>;
					phandle = <0x37>;
				};

				endpoint@2 {
					reg = <0x02>;
					remote-endpoint = <0xc8>;
					phandle = <0xe2>;
				};

				endpoint@3 {
					reg = <0x03>;
					remote-endpoint = <0xc9>;
					phandle = <0xd0>;
				};

				endpoint@4 {
					reg = <0x04>;
					remote-endpoint = <0xca>;
					phandle = <0xd5>;
				};
			};

			port@3 {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				reg = <0x03>;
				cursor-win-id = <0x07>;
				rockchip,plane-mask = <0x280>;
				rockchip,primary-plane = <0x09>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xcb>;
					phandle = <0x35>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xcc>;
					phandle = <0x36>;
				};

				endpoint@2 {
					reg = <0x02>;
					remote-endpoint = <0xcd>;
					phandle = <0x39>;
				};
			};
		};
	};

	iommu@fdd97e00 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdd97e00 0x00 0x100 0x00 0xfdd97f00 0x00 0x100>;
		interrupts = <0x00 0x9c 0x04>;
		interrupt-names = "vop_mmu";
		clocks = <0x02 0x270 0x02 0x26f>;
		clock-names = "aclk\0iface";
		#iommu-cells = <0x00>;
		rockchip,disable-device-link-resume;
		rockchip,shootdown-entire;
		status = "okay";
		phandle = <0xbc>;
	};

	spdif-tx@fddb0000 {
		compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif";
		reg = <0x00 0xfddb0000 0x00 0x1000>;
		interrupts = <0x00 0xc3 0x04>;
		dmas = <0xce 0x06>;
		dma-names = "tx";
		clock-names = "mclk\0hclk";
		clocks = <0x02 0x209 0x02 0x204>;
		assigned-clocks = <0x02 0x205>;
		assigned-clock-parents = <0x02 0x05>;
		power-domains = <0x4f 0x19>;
		#sound-dai-cells = <0x00>;
		status = "okay";
		phandle = <0x177>;
	};

	i2s@fddc0000 {
		compatible = "rockchip,rk3588-i2s-tdm";
		reg = <0x00 0xfddc0000 0x00 0x1000>;
		interrupts = <0x00 0xb8 0x04>;
		clocks = <0x02 0x1fb 0x02 0x1fb 0x02 0x1f0>;
		clock-names = "mclk_tx\0mclk_rx\0hclk";
		assigned-clocks = <0x02 0x1f9>;
		assigned-clock-parents = <0x02 0x05>;
		dmas = <0xcf 0x00>;
		dma-names = "tx";
		power-domains = <0x4f 0x19>;
		resets = <0x02 0x38d>;
		reset-names = "tx-m";
		rockchip,playback-only;
		#sound-dai-cells = <0x00>;
		status = "disabled";
	};

	spdif-tx@fdde0000 {
		compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif";
		reg = <0x00 0xfdde0000 0x00 0x1000>;
		interrupts = <0x00 0xc4 0x04>;
		dmas = <0xce 0x07>;
		dma-names = "tx";
		clock-names = "mclk\0hclk";
		clocks = <0x02 0x257 0x02 0x253>;
		assigned-clocks = <0x02 0x254>;
		assigned-clock-parents = <0x02 0x05>;
		power-domains = <0x4f 0x1a>;
		#sound-dai-cells = <0x00>;
		status = "disabled";
	};

	i2s@fddf0000 {
		compatible = "rockchip,rk3588-i2s-tdm";
		reg = <0x00 0xfddf0000 0x00 0x1000>;
		interrupts = <0x00 0xb9 0x04>;
		clocks = <0x02 0x246 0x02 0x246 0x02 0x248>;
		clock-names = "mclk_tx\0mclk_rx\0hclk";
		assigned-clocks = <0x02 0x243>;
		assigned-clock-parents = <0x02 0x07>;
		dmas = <0xcf 0x02>;
		dma-names = "tx";
		power-domains = <0x4f 0x1a>;
		resets = <0x02 0x3e8>;
		reset-names = "tx-m";
		rockchip,always-on;
		rockchip,hdmi-path;
		rockchip,playback-only;
		#sound-dai-cells = <0x00>;
		status = "okay";
		phandle = <0x179>;
	};

	i2s@fddfc000 {
		compatible = "rockchip,rk3588-i2s-tdm";
		reg = <0x00 0xfddfc000 0x00 0x1000>;
		interrupts = <0x00 0xbd 0x04>;
		clocks = <0x02 0x242 0x02 0x242 0x02 0x23e>;
		clock-names = "mclk_tx\0mclk_rx\0hclk";
		assigned-clocks = <0x02 0x23f>;
		assigned-clock-parents = <0x02 0x05>;
		dmas = <0xcf 0x17>;
		dma-names = "rx";
		power-domains = <0x4f 0x1a>;
		resets = <0x02 0x413>;
		reset-names = "rx-m";
		rockchip,capture-only;
		#sound-dai-cells = <0x00>;
		status = "disabled";
	};

	spdif-rx@fde08000 {
		compatible = "rockchip,rk3588-spdifrx\0rockchip,rk3308-spdifrx";
		reg = <0x00 0xfde08000 0x00 0x1000>;
		interrupts = <0x00 0xc7 0x04>;
		clocks = <0x02 0x25e 0x02 0x25d>;
		clock-names = "mclk\0hclk";
		assigned-clocks = <0x02 0x25e>;
		assigned-clock-parents = <0x02 0x05>;
		dmas = <0x66 0x15>;
		dma-names = "rx";
		power-domains = <0x4f 0x1a>;
		resets = <0x02 0x3fd>;
		reset-names = "spdifrx-m";
		#sound-dai-cells = <0x00>;
		status = "disabled";
	};

	dsi@fde20000 {
		compatible = "rockchip,rk3588-mipi-dsi2";
		reg = <0x00 0xfde20000 0x00 0x10000>;
		interrupts = <0x00 0xa7 0x04>;
		clocks = <0x02 0x278 0x02 0x27a>;
		clock-names = "pclk\0sys_clk";
		resets = <0x02 0x354>;
		reset-names = "apb";
		power-domains = <0x4f 0x18>;
		phys = <0x2a>;
		phy-names = "dcphy";
		rockchip,grf = <0xbd>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xd0>;
					status = "disabled";
					phandle = <0xc9>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0x35>;
					status = "disabled";
					phandle = <0xcb>;
				};
			};

			port@1 {
				reg = <0x01>;

				endpoint {
					remote-endpoint = <0xd1>;
					phandle = <0xd4>;
				};
			};
		};

		panel@0 {
			status = "okay";
			compatible = "simple-panel-dsi";
			reg = <0x00>;
			backlight = <0xd2>;
			reset-delay-ms = <0x3c>;
			enable-delay-ms = <0x3c>;
			prepare-delay-ms = <0x3c>;
			unprepare-delay-ms = <0x3c>;
			disable-delay-ms = <0x3c>;
			dsi,flags = <0xa03>;
			dsi,format = <0x00>;
			dsi,lanes = <0x02>;
			panel-init-sequence = <0x2300027a 0xc1230002 0x20202300 0x221e023 0x22213 0x23000223 0x8230002 0x24042300 0x2250823 0x22600 0x23000227 0x8230002 0x28042300 0x2290823 0x23480 0x23000286 0x29230002 0xb5a02300 0x25cff23 0x22a01 0x23000256 0x92230002 0x6b712300 0x2691523 0x21040 0x23000211 0x88230002 0xb6202300 0x2512023 0x20910 0x5780111 0x51e0129>;
			panel-exit-sequence = <0x5000128 0x5000110>;

			display-timings {
				native-mode = <0xd3>;

				timing0 {
					clock-frequency = <0x17d7840>;
					hactive = <0x320>;
					vactive = <0x1e0>;
					hfront-porch = <0x08>;
					hsync-len = <0x04>;
					hback-porch = <0x08>;
					vfront-porch = <0x08>;
					vsync-len = <0x04>;
					vback-porch = <0x08>;
					hsync-active = <0x00>;
					vsync-active = <0x00>;
					de-active = <0x00>;
					pixelclk-active = <0x00>;
					phandle = <0xd3>;
				};
			};

			ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				port@0 {
					reg = <0x00>;

					endpoint {
						remote-endpoint = <0xd4>;
						phandle = <0xd1>;
					};
				};
			};
		};
	};

	dsi@fde30000 {
		compatible = "rockchip,rk3588-mipi-dsi2";
		reg = <0x00 0xfde30000 0x00 0x10000>;
		interrupts = <0x00 0xa8 0x04>;
		clocks = <0x02 0x279 0x02 0x27b>;
		clock-names = "pclk\0sys_clk";
		resets = <0x02 0x355>;
		reset-names = "apb";
		power-domains = <0x4f 0x18>;
		phys = <0x2b>;
		phy-names = "dcphy";
		rockchip,grf = <0xbd>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xd5>;
					status = "disabled";
					phandle = <0xca>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0x36>;
					status = "disabled";
					phandle = <0xcc>;
				};
			};
		};
	};

	hdcp@fde40000 {
		compatible = "rockchip,rk3588-hdcp";
		reg = <0x00 0xfde40000 0x00 0x80>;
		interrupts = <0x00 0x9f 0x04>;
		clocks = <0x02 0x1ed 0x02 0x1ef 0x02 0x1ee 0x02 0x1ec 0x02 0x1f1 0x02 0x1f2>;
		clock-names = "aclk\0pclk\0hclk\0hclk_key\0aclk_trng\0pclk_trng";
		resets = <0x02 0x37f 0x02 0x37d 0x02 0x37c 0x02 0x37b 0x02 0x381>;
		reset-names = "hdcp\0h_hdcp\0a_hdcp\0hdcp_key\0trng";
		power-domains = <0x4f 0x19>;
		rockchip,vo-grf = <0xd6>;
		status = "disabled";
	};

	dp@fde50000 {
		compatible = "rockchip,rk3588-dp";
		reg = <0x00 0xfde50000 0x00 0x4000>;
		interrupts = <0x00 0xa1 0x04>;
		clocks = <0x02 0x1e6 0x02 0x2cc 0x02 0x1fb 0x02 0x207 0x04>;
		clock-names = "apb\0aux\0i2s\0spdif\0hclk";
		assigned-clocks = <0x02 0x2cc>;
		assigned-clock-rates = <0xf42400>;
		resets = <0x02 0x388>;
		phys = <0xd7>;
		power-domains = <0x4f 0x19>;
		#sound-dai-cells = <0x01>;
		status = "okay";
		pinctrl-0 = <0xd8>;
		pinctrl-names = "default";
		phandle = <0x178>;

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xd9>;
					status = "disabled";
					phandle = <0xc0>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0x34>;
					status = "disabled";
					phandle = <0xc3>;
				};

				endpoint@2 {
					reg = <0x02>;
					remote-endpoint = <0xda>;
					status = "okay";
					phandle = <0xc6>;
				};
			};
		};
	};

	hdcp@fde70000 {
		compatible = "rockchip,rk3588-hdcp";
		reg = <0x00 0xfde70000 0x00 0x80>;
		interrupts = <0x00 0xa0 0x04>;
		clocks = <0x02 0x217 0x02 0x219 0x02 0x218 0x02 0x216 0x02 0x228 0x02 0x229>;
		clock-names = "aclk\0pclk\0hclk\0hclk_key\0aclk_trng\0pclk_trng";
		resets = <0x02 0x3c8 0x02 0x3c6 0x02 0x3c5 0x02 0x3c4 0x02 0x3ca>;
		reset-names = "hdcp\0h_hdcp\0a_hdcp\0hdcp_key\0trng";
		power-domains = <0x4f 0x1a>;
		rockchip,vo-grf = <0xbe>;
		status = "disabled";
	};

	hdmi@fde80000 {
		compatible = "rockchip,rk3588-dw-hdmi";
		reg = <0x00 0xfde80000 0x00 0x20000>;
		interrupts = <0x00 0xa9 0x04 0x00 0xaa 0x04 0x00 0xab 0x04 0x00 0xac 0x04 0x00 0x168 0x04>;
		clocks = <0x02 0x221 0x02 0x265 0x02 0x222 0x02 0x223 0x02 0x246 0x02 0x274 0x02 0x275 0x02 0x276 0x02 0x277 0x05 0x32>;
		clock-names = "pclk\0hpd\0earc\0hdmitx_ref\0aud\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0hclk_vo1\0link_clk";
		resets = <0x02 0x3d0 0x02 0x49c>;
		reset-names = "ref\0hdp";
		power-domains = <0x4f 0x1a>;
		pinctrl-names = "default";
		pinctrl-0 = <0xdb 0xdc 0xdd 0xde>;
		reg-io-width = <0x04>;
		rockchip,grf = <0xb9>;
		rockchip,vo1_grf = <0xbe>;
		phys = <0xdf>;
		phy-names = "hdmi";
		#sound-dai-cells = <0x00>;
		status = "okay";
		enable-gpios = <0xe0 0x0e 0x00>;
		phandle = <0x17a>;

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0x38>;
					status = "okay";
					phandle = <0xc2>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xe1>;
					status = "okay";
					phandle = <0xc5>;
				};

				endpoint@2 {
					reg = <0x02>;
					remote-endpoint = <0xe2>;
					status = "disabled";
					phandle = <0xc8>;
				};
			};
		};
	};

	edp@fdec0000 {
		compatible = "rockchip,rk3588-edp";
		reg = <0x00 0xfdec0000 0x00 0x1000>;
		interrupts = <0x00 0xa3 0x04>;
		clocks = <0x02 0x211 0x02 0x210 0x02 0x212 0x05>;
		clock-names = "dp\0pclk\0spdif\0hclk";
		resets = <0x02 0x3e1 0x02 0x3e0>;
		reset-names = "dp\0apb";
		phys = <0xe3>;
		phy-names = "dp";
		power-domains = <0x4f 0x1a>;
		rockchip,grf = <0xbe>;
		status = "disabled";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xe4>;
					status = "disabled";
					phandle = <0xc1>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xe5>;
					status = "disabled";
					phandle = <0xc4>;
				};

				endpoint@2 {
					reg = <0x02>;
					remote-endpoint = <0x37>;
					status = "disabled";
					phandle = <0xc7>;
				};
			};
		};
	};

	qos@fdf35000 {
		compatible = "syscon";
		reg = <0x00 0xfdf35000 0x00 0x20>;
		phandle = <0x71>;
	};

	qos@fdf35200 {
		compatible = "syscon";
		reg = <0x00 0xfdf35200 0x00 0x20>;
		phandle = <0x72>;
	};

	qos@fdf35400 {
		compatible = "syscon";
		reg = <0x00 0xfdf35400 0x00 0x20>;
		phandle = <0x73>;
	};

	qos@fdf35600 {
		compatible = "syscon";
		reg = <0x00 0xfdf35600 0x00 0x20>;
		phandle = <0x74>;
	};

	qos@fdf36000 {
		compatible = "syscon";
		reg = <0x00 0xfdf36000 0x00 0x20>;
		phandle = <0x94>;
	};

	qos@fdf39000 {
		compatible = "syscon";
		reg = <0x00 0xfdf39000 0x00 0x20>;
		phandle = <0x99>;
	};

	qos@fdf3d800 {
		compatible = "syscon";
		reg = <0x00 0xfdf3d800 0x00 0x20>;
		phandle = <0x9a>;
	};

	qos@fdf3e000 {
		compatible = "syscon";
		reg = <0x00 0xfdf3e000 0x00 0x20>;
		phandle = <0x96>;
	};

	qos@fdf3e200 {
		compatible = "syscon";
		reg = <0x00 0xfdf3e200 0x00 0x20>;
		phandle = <0x95>;
	};

	qos@fdf3e400 {
		compatible = "syscon";
		reg = <0x00 0xfdf3e400 0x00 0x20>;
		phandle = <0x97>;
	};

	qos@fdf3e600 {
		compatible = "syscon";
		reg = <0x00 0xfdf3e600 0x00 0x20>;
		phandle = <0x98>;
	};

	qos@fdf40000 {
		compatible = "syscon";
		reg = <0x00 0xfdf40000 0x00 0x20>;
		phandle = <0x92>;
	};

	qos@fdf40200 {
		compatible = "syscon";
		reg = <0x00 0xfdf40200 0x00 0x20>;
		phandle = <0x93>;
	};

	qos@fdf40400 {
		compatible = "syscon";
		reg = <0x00 0xfdf40400 0x00 0x20>;
		phandle = <0x8c>;
	};

	qos@fdf40500 {
		compatible = "syscon";
		reg = <0x00 0xfdf40500 0x00 0x20>;
		phandle = <0x8d>;
	};

	qos@fdf40600 {
		compatible = "syscon";
		reg = <0x00 0xfdf40600 0x00 0x20>;
		phandle = <0x8e>;
	};

	qos@fdf40800 {
		compatible = "syscon";
		reg = <0x00 0xfdf40800 0x00 0x20>;
		phandle = <0x8f>;
	};

	qos@fdf41000 {
		compatible = "syscon";
		reg = <0x00 0xfdf41000 0x00 0x20>;
		phandle = <0x90>;
	};

	qos@fdf41100 {
		compatible = "syscon";
		reg = <0x00 0xfdf41100 0x00 0x20>;
		phandle = <0x91>;
	};

	qos@fdf60000 {
		compatible = "syscon";
		reg = <0x00 0xfdf60000 0x00 0x20>;
		phandle = <0x77>;
	};

	qos@fdf60200 {
		compatible = "syscon";
		reg = <0x00 0xfdf60200 0x00 0x20>;
		phandle = <0x78>;
	};

	qos@fdf60400 {
		compatible = "syscon";
		reg = <0x00 0xfdf60400 0x00 0x20>;
		phandle = <0x79>;
	};

	qos@fdf61000 {
		compatible = "syscon";
		reg = <0x00 0xfdf61000 0x00 0x20>;
		phandle = <0x7a>;
	};

	qos@fdf61200 {
		compatible = "syscon";
		reg = <0x00 0xfdf61200 0x00 0x20>;
		phandle = <0x7b>;
	};

	qos@fdf61400 {
		compatible = "syscon";
		reg = <0x00 0xfdf61400 0x00 0x20>;
		phandle = <0x7c>;
	};

	qos@fdf62000 {
		compatible = "syscon";
		reg = <0x00 0xfdf62000 0x00 0x20>;
		phandle = <0x75>;
	};

	qos@fdf63000 {
		compatible = "syscon";
		reg = <0x00 0xfdf63000 0x00 0x20>;
		phandle = <0x76>;
	};

	qos@fdf64000 {
		compatible = "syscon";
		reg = <0x00 0xfdf64000 0x00 0x20>;
		phandle = <0x85>;
	};

	qos@fdf66000 {
		compatible = "syscon";
		reg = <0x00 0xfdf66000 0x00 0x20>;
		phandle = <0x7d>;
	};

	qos@fdf66200 {
		compatible = "syscon";
		reg = <0x00 0xfdf66200 0x00 0x20>;
		phandle = <0x7e>;
	};

	qos@fdf66400 {
		compatible = "syscon";
		reg = <0x00 0xfdf66400 0x00 0x20>;
		phandle = <0x7f>;
	};

	qos@fdf66600 {
		compatible = "syscon";
		reg = <0x00 0xfdf66600 0x00 0x20>;
		phandle = <0x80>;
	};

	qos@fdf66800 {
		compatible = "syscon";
		reg = <0x00 0xfdf66800 0x00 0x20>;
		phandle = <0x81>;
	};

	qos@fdf66a00 {
		compatible = "syscon";
		reg = <0x00 0xfdf66a00 0x00 0x20>;
		phandle = <0x82>;
	};

	qos@fdf66c00 {
		compatible = "syscon";
		reg = <0x00 0xfdf66c00 0x00 0x20>;
		phandle = <0x83>;
	};

	qos@fdf66e00 {
		compatible = "syscon";
		reg = <0x00 0xfdf66e00 0x00 0x20>;
		phandle = <0x84>;
	};

	qos@fdf67000 {
		compatible = "syscon";
		reg = <0x00 0xfdf67000 0x00 0x20>;
		phandle = <0x86>;
	};

	qos@fdf67200 {
		compatible = "syscon";
		reg = <0x00 0xfdf67200 0x00 0x20>;
	};

	qos@fdf70000 {
		compatible = "syscon";
		reg = <0x00 0xfdf70000 0x00 0x20>;
		phandle = <0x6f>;
	};

	qos@fdf71000 {
		compatible = "syscon";
		reg = <0x00 0xfdf71000 0x00 0x20>;
		phandle = <0x70>;
	};

	qos@fdf72000 {
		compatible = "syscon";
		reg = <0x00 0xfdf72000 0x00 0x20>;
		phandle = <0x6c>;
	};

	qos@fdf72200 {
		compatible = "syscon";
		reg = <0x00 0xfdf72200 0x00 0x20>;
		phandle = <0x6d>;
	};

	qos@fdf72400 {
		compatible = "syscon";
		reg = <0x00 0xfdf72400 0x00 0x20>;
		phandle = <0x6e>;
	};

	qos@fdf80000 {
		compatible = "syscon";
		reg = <0x00 0xfdf80000 0x00 0x20>;
		phandle = <0x89>;
	};

	qos@fdf81000 {
		compatible = "syscon";
		reg = <0x00 0xfdf81000 0x00 0x20>;
		phandle = <0x8a>;
	};

	qos@fdf81200 {
		compatible = "syscon";
		reg = <0x00 0xfdf81200 0x00 0x20>;
		phandle = <0x8b>;
	};

	qos@fdf82000 {
		compatible = "syscon";
		reg = <0x00 0xfdf82000 0x00 0x20>;
		phandle = <0x87>;
	};

	qos@fdf82200 {
		compatible = "syscon";
		reg = <0x00 0xfdf82200 0x00 0x20>;
		phandle = <0x88>;
	};

	dfi@fe060000 {
		compatible = "rockchip,rk3588-dfi";
		reg = <0x00 0xfe060000 0x00 0x10000>;
		rockchip,pmu_grf = <0xe6>;
		status = "disabled";
		phandle = <0x3a>;
	};

	pcie@fe180000 {
		compatible = "rockchip,rk3588-pcie\0snps,dw-pcie";
		#address-cells = <0x03>;
		#size-cells = <0x02>;
		bus-range = <0x30 0x3f>;
		clocks = <0x02 0x151 0x02 0x156 0x02 0x14c 0x02 0x15c 0x02 0x161 0x02 0x2c5>;
		clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe";
		device_type = "pci";
		interrupts = <0x00 0xf8 0x04 0x00 0xf7 0x04 0x00 0xf6 0x04 0x00 0xf5 0x04 0x00 0xf4 0x04>;
		interrupt-names = "sys\0pmc\0msg\0legacy\0err";
		#interrupt-cells = <0x01>;
		interrupt-map-mask = <0x00 0x00 0x00 0x07>;
		interrupt-map = <0x00 0x00 0x00 0x01 0xe7 0x00 0x00 0x00 0x00 0x02 0xe7 0x01 0x00 0x00 0x00 0x03 0xe7 0x02 0x00 0x00 0x00 0x04 0xe7 0x03>;
		linux,pci-domain = <0x03>;
		num-ib-windows = <0x08>;
		num-ob-windows = <0x08>;
		num-viewport = <0x04>;
		max-link-speed = <0x02>;
		msi-map = <0x3000 0xe8 0x3000 0x1000>;
		num-lanes = <0x01>;
		phys = <0x5c 0x02>;
		phy-names = "pcie-phy";
		ranges = <0x800 0x00 0xf3000000 0x00 0xf3000000 0x00 0x100000 0x81000000 0x00 0xf3100000 0x00 0xf3100000 0x00 0x100000 0x82000000 0x00 0xf3200000 0x00 0xf3200000 0x00 0xe00000 0xc3000000 0x09 0xc0000000 0x09 0xc0000000 0x00 0x40000000>;
		reg = <0x00 0xfe180000 0x00 0x10000 0x0a 0x40c00000 0x00 0x400000>;
		reg-names = "pcie-apb\0pcie-dbi";
		resets = <0x02 0x210 0x02 0x21f>;
		reset-names = "pcie\0periph";
		rockchip,pipe-grf = <0x63>;
		status = "disabled";
		reset-gpios = <0xe0 0x02 0x00>;

		legacy-interrupt-controller {
			interrupt-controller;
			#address-cells = <0x00>;
			#interrupt-cells = <0x01>;
			interrupt-parent = <0x01>;
			interrupts = <0x00 0xf5 0x01>;
			phandle = <0xe7>;
		};
	};

	pcie@fe190000 {
		compatible = "rockchip,rk3588-pcie\0snps,dw-pcie";
		#address-cells = <0x03>;
		#size-cells = <0x02>;
		bus-range = <0x40 0x4f>;
		clocks = <0x02 0x152 0x02 0x157 0x02 0x14d 0x02 0x15d 0x02 0x162 0x02 0x182>;
		clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe";
		device_type = "pci";
		interrupts = <0x00 0xfd 0x04 0x00 0xfc 0x04 0x00 0xfb 0x04 0x00 0xfa 0x04 0x00 0xf9 0x04>;
		interrupt-names = "sys\0pmc\0msg\0legacy\0err";
		#interrupt-cells = <0x01>;
		interrupt-map-mask = <0x00 0x00 0x00 0x07>;
		interrupt-map = <0x00 0x00 0x00 0x01 0xe9 0x00 0x00 0x00 0x00 0x02 0xe9 0x01 0x00 0x00 0x00 0x03 0xe9 0x02 0x00 0x00 0x00 0x04 0xe9 0x03>;
		linux,pci-domain = <0x04>;
		num-ib-windows = <0x08>;
		num-ob-windows = <0x08>;
		num-viewport = <0x04>;
		max-link-speed = <0x02>;
		msi-map = <0x4000 0xe8 0x4000 0x1000>;
		num-lanes = <0x01>;
		phys = <0xea 0x02>;
		phy-names = "pcie-phy";
		ranges = <0x800 0x00 0xf4000000 0x00 0xf4000000 0x00 0x100000 0x81000000 0x00 0xf4100000 0x00 0xf4100000 0x00 0x100000 0x82000000 0x00 0xf4200000 0x00 0xf4200000 0x00 0xe00000 0xc3000000 0x0a 0x00 0x0a 0x00 0x00 0x40000000>;
		reg = <0x00 0xfe190000 0x00 0x10000 0x0a 0x41000000 0x00 0x400000>;
		reg-names = "pcie-apb\0pcie-dbi";
		resets = <0x02 0x211 0x02 0x220>;
		reset-names = "pcie\0periph";
		rockchip,pipe-grf = <0x63>;
		status = "okay";
		reset-gpios = <0xeb 0x19 0x00>;
		rockchip,skip-scan-in-resume;
		pinctrl-names = "default";
		pinctrl-0 = <0xec>;

		legacy-interrupt-controller {
			interrupt-controller;
			#address-cells = <0x00>;
			#interrupt-cells = <0x01>;
			interrupt-parent = <0x01>;
			interrupts = <0x00 0xfa 0x01>;
			phandle = <0xe9>;
		};
	};

	ethernet@fe1c0000 {
		compatible = "rockchip,rk3588-gmac\0snps,dwmac-4.20a";
		reg = <0x00 0xfe1c0000 0x00 0x10000>;
		interrupts = <0x00 0xea 0x04 0x00 0xe9 0x04>;
		interrupt-names = "macirq\0eth_wake_irq";
		rockchip,grf = <0xb9>;
		rockchip,php_grf = <0x63>;
		clocks = <0x02 0x144 0x02 0x145 0x02 0x168 0x02 0x16d 0x02 0x143>;
		clock-names = "stmmaceth\0clk_mac_ref\0pclk_mac\0aclk_mac\0ptp_ref";
		resets = <0x02 0x20b>;
		reset-names = "stmmaceth";
		power-domains = <0x4f 0x21>;
		snps,mixed-burst;
		snps,tso;
		snps,axi-config = <0xed>;
		snps,mtl-rx-config = <0xee>;
		snps,mtl-tx-config = <0xef>;
		status = "disabled";

		mdio {
			compatible = "snps,dwmac-mdio";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
		};

		stmmac-axi-config {
			snps,wr_osr_lmt = <0x04>;
			snps,rd_osr_lmt = <0x08>;
			snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
			phandle = <0xed>;
		};

		rx-queues-config {
			snps,rx-queues-to-use = <0x02>;
			phandle = <0xee>;

			queue0 {
			};

			queue1 {
			};
		};

		tx-queues-config {
			snps,tx-queues-to-use = <0x02>;
			phandle = <0xef>;

			queue0 {
			};

			queue1 {
			};
		};
	};

	sata@fe210000 {
		compatible = "rockchip,rk-ahci\0snps,dwc-ahci";
		reg = <0x00 0xfe210000 0x00 0x1000>;
		clocks = <0x02 0x171 0x02 0x16e 0x02 0x174 0x02 0x163 0x02 0x17e>;
		clock-names = "sata\0pmalive\0rxoob\0ref\0asic";
		interrupts = <0x00 0x111 0x04>;
		interrupt-names = "hostc";
		phys = <0xea 0x01>;
		phy-names = "sata-phy";
		ports-implemented = <0x01>;
		status = "disabled";
	};

	sata@fe230000 {
		compatible = "rockchip,rk-ahci\0snps,dwc-ahci";
		reg = <0x00 0xfe230000 0x00 0x1000>;
		clocks = <0x02 0x173 0x02 0x170 0x02 0x176 0x02 0x165 0x02 0x180>;
		clock-names = "sata\0pmalive\0rxoob\0ref\0asic";
		interrupts = <0x00 0x113 0x04>;
		interrupt-names = "hostc";
		phys = <0x5c 0x01>;
		phy-names = "sata-phy";
		ports-implemented = <0x01>;
		status = "disabled";
	};

	spi@fe2b0000 {
		compatible = "rockchip,sfc";
		reg = <0x00 0xfe2b0000 0x00 0x4000>;
		interrupts = <0x00 0xce 0x04>;
		clocks = <0x02 0x13d 0x02 0x13e>;
		clock-names = "clk_sfc\0hclk_sfc";
		assigned-clocks = <0x02 0x13d>;
		assigned-clock-rates = <0x5f5e100>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	mmc@fe2c0000 {
		compatible = "rockchip,rk3588-dw-mshc\0rockchip,rk3288-dw-mshc";
		reg = <0x00 0xfe2c0000 0x00 0x4000>;
		interrupts = <0x00 0xcb 0x04>;
		clocks = <0x0e 0x17 0x0e 0x09 0x02 0x2c2 0x02 0x2c3>;
		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
		fifo-depth = <0x100>;
		max-frequency = <0x8f0d180>;
		pinctrl-names = "default";
		pinctrl-0 = <0xf0 0xf1 0xf2 0xf3>;
		power-domains = <0x4f 0x28>;
		status = "okay";
		no-sdio;
		no-mmc;
		bus-width = <0x04>;
		cap-mmc-highspeed;
		cap-sd-highspeed;
		disable-wp;
		sd-uhs-sdr104;
		vmmc-supply = <0xf4>;
		vqmmc-supply = <0xf5>;
	};

	mmc@fe2d0000 {
		compatible = "rockchip,rk3588-dw-mshc\0rockchip,rk3288-dw-mshc";
		reg = <0x00 0xfe2d0000 0x00 0x4000>;
		interrupts = <0x00 0xcc 0x04>;
		clocks = <0x02 0x199 0x02 0x19a 0x02 0x2c0 0x02 0x2c1>;
		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
		fifo-depth = <0x100>;
		max-frequency = <0x8f0d180>;
		pinctrl-names = "default";
		pinctrl-0 = <0xf6 0xf7>;
		power-domains = <0x4f 0x25>;
		status = "okay";
		no-sd;
		no-mmc;
		bus-width = <0x04>;
		disable-wp;
		cap-sd-highspeed;
		cap-sdio-irq;
		keep-power-in-suspend;
		mmc-pwrseq = <0xf8>;
		non-removable;
	};

	mmc@fe2e0000 {
		compatible = "rockchip,rk3588-dwcmshc\0rockchip,dwcmshc-sdhci";
		reg = <0x00 0xfe2e0000 0x00 0x10000>;
		interrupts = <0x00 0xcd 0x04>;
		assigned-clocks = <0x02 0x13b 0x02 0x13c 0x02 0x13a>;
		assigned-clock-rates = <0xbebc200 0x16e3600 0xbebc200>;
		clocks = <0x02 0x13a 0x02 0x138 0x02 0x139 0x02 0x13b 0x02 0x13c>;
		clock-names = "core\0bus\0axi\0block\0timer";
		resets = <0x02 0x1f6 0x02 0x1f4 0x02 0x1f5 0x02 0x1f7 0x02 0x1f8>;
		reset-names = "core\0bus\0axi\0block\0timer";
		max-frequency = <0xbebc200>;
		status = "okay";
		bus-width = <0x08>;
		no-sdio;
		no-sd;
		non-removable;
		mmc-hs400-1_8v;
		mmc-hs400-enhanced-strobe;
	};

	crypto@fe370000 {
		compatible = "rockchip,rk3588-crypto";
		reg = <0x00 0xfe370000 0x00 0x2000>;
		interrupts = <0x00 0xd1 0x04>;
		clocks = <0x0e 0x0b 0x0e 0x0c 0x0e 0x14 0x0e 0x15>;
		clock-names = "aclk\0hclk\0sclk\0pka";
		resets = <0xf9 0x0f>;
		reset-names = "crypto-rst";
		status = "disabled";
	};

	rng@fe378000 {
		compatible = "rockchip,trngv1";
		reg = <0x00 0xfe378000 0x00 0x200>;
		interrupts = <0x00 0x190 0x04>;
		clocks = <0x0e 0x0c>;
		clock-names = "hclk_trng";
		resets = <0xf9 0x30>;
		reset-names = "reset";
		status = "disabled";
	};

	i2s@fe470000 {
		compatible = "rockchip,rk3588-i2s-tdm";
		reg = <0x00 0xfe470000 0x00 0x1000>;
		interrupts = <0x00 0xb4 0x04>;
		clocks = <0x02 0x33 0x02 0x37 0x02 0x30>;
		clock-names = "mclk_tx\0mclk_rx\0hclk";
		assigned-clocks = <0x02 0x31 0x02 0x35>;
		assigned-clock-parents = <0x02 0x05 0x02 0x05>;
		dmas = <0x66 0x00 0x66 0x01>;
		dma-names = "tx\0rx";
		power-domains = <0x4f 0x26>;
		resets = <0x02 0x77 0x02 0x7a>;
		reset-names = "tx-m\0rx-m";
		rockchip,clk-trcm = <0x01>;
		pinctrl-names = "default";
		pinctrl-0 = <0xfa 0xfb 0xfc 0xfd>;
		#sound-dai-cells = <0x00>;
		status = "okay";
		phandle = <0x17b>;
	};

	i2s@fe480000 {
		compatible = "rockchip,rk3588-i2s-tdm";
		reg = <0x00 0xfe480000 0x00 0x1000>;
		interrupts = <0x00 0xb5 0x04>;
		clocks = <0x02 0x28c 0x02 0x290 0x02 0x288>;
		clock-names = "mclk_tx\0mclk_rx\0hclk";
		dmas = <0x66 0x02 0x66 0x03>;
		dma-names = "tx\0rx";
		resets = <0x02 0xc002a 0x02 0xc002d>;
		reset-names = "tx-m\0rx-m";
		rockchip,clk-trcm = <0x01>;
		pinctrl-names = "default";
		pinctrl-0 = <0xfe 0xff 0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107>;
		#sound-dai-cells = <0x00>;
		status = "disabled";
	};

	i2s@fe490000 {
		compatible = "rockchip,rk3588-i2s\0rockchip,rk3066-i2s";
		reg = <0x00 0xfe490000 0x00 0x1000>;
		interrupts = <0x00 0xb6 0x04>;
		clocks = <0x02 0x27 0x02 0x22>;
		clock-names = "i2s_clk\0i2s_hclk";
		assigned-clocks = <0x02 0x24>;
		assigned-clock-parents = <0x02 0x05>;
		dmas = <0xce 0x00 0xce 0x01>;
		dma-names = "tx\0rx";
		power-domains = <0x4f 0x26>;
		rockchip,clk-trcm = <0x01>;
		pinctrl-names = "default";
		pinctrl-0 = <0x108 0x109 0x10a 0x10b>;
		#sound-dai-cells = <0x00>;
		status = "disabled";
	};

	i2s@fe4a0000 {
		compatible = "rockchip,rk3588-i2s\0rockchip,rk3066-i2s";
		reg = <0x00 0xfe4a0000 0x00 0x1000>;
		interrupts = <0x00 0xb7 0x04>;
		clocks = <0x02 0x2d 0x02 0x23>;
		clock-names = "i2s_clk\0i2s_hclk";
		assigned-clocks = <0x02 0x2a>;
		assigned-clock-parents = <0x02 0x05>;
		dmas = <0xce 0x02 0xce 0x03>;
		dma-names = "tx\0rx";
		power-domains = <0x4f 0x26>;
		rockchip,clk-trcm = <0x01>;
		pinctrl-names = "default";
		pinctrl-0 = <0x10c 0x10d 0x10e 0x10f>;
		#sound-dai-cells = <0x00>;
		status = "disabled";
	};

	pdm@fe4b0000 {
		compatible = "rockchip,rk3588-pdm";
		reg = <0x00 0xfe4b0000 0x00 0x1000>;
		clocks = <0x02 0x29f 0x02 0x29e>;
		clock-names = "pdm_clk\0pdm_hclk";
		dmas = <0x66 0x04>;
		dma-names = "rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x110 0x111 0x112 0x113 0x114 0x115>;
		#sound-dai-cells = <0x00>;
		status = "disabled";
	};

	pdm@fe4c0000 {
		compatible = "rockchip,rk3588-pdm";
		reg = <0x00 0xfe4c0000 0x00 0x1000>;
		clocks = <0x02 0x3b 0x02 0x3a>;
		clock-names = "pdm_clk\0pdm_hclk";
		assigned-clocks = <0x02 0x3b>;
		assigned-clock-parents = <0x02 0x05>;
		dmas = <0xce 0x04>;
		dma-names = "rx";
		power-domains = <0x4f 0x26>;
		pinctrl-names = "default";
		pinctrl-0 = <0x116 0x117 0x118 0x119 0x11a 0x11b>;
		#sound-dai-cells = <0x00>;
		status = "disabled";
	};

	vad@fe4d0000 {
		compatible = "rockchip,rk3588-vad";
		reg = <0x00 0xfe4d0000 0x00 0x1000>;
		reg-names = "vad";
		clocks = <0x02 0x2a0>;
		clock-names = "hclk";
		interrupts = <0x00 0xca 0x04>;
		rockchip,audio-src = <0x00>;
		rockchip,det-channel = <0x00>;
		rockchip,mode = <0x00>;
		#sound-dai-cells = <0x00>;
		status = "disabled";
	};

	spdif-tx@fe4e0000 {
		compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif";
		reg = <0x00 0xfe4e0000 0x00 0x1000>;
		interrupts = <0x00 0xc1 0x04>;
		dmas = <0x66 0x05>;
		dma-names = "tx";
		clock-names = "mclk\0hclk";
		clocks = <0x02 0x41 0x02 0x3e>;
		assigned-clocks = <0x02 0x3f>;
		assigned-clock-parents = <0x02 0x05>;
		power-domains = <0x4f 0x26>;
		pinctrl-names = "default";
		pinctrl-0 = <0x11c>;
		#sound-dai-cells = <0x00>;
		status = "disabled";
	};

	spdif-tx@fe4f0000 {
		compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif";
		reg = <0x00 0xfe4f0000 0x00 0x1000>;
		interrupts = <0x00 0xc2 0x04>;
		dmas = <0xce 0x05>;
		dma-names = "tx";
		clock-names = "mclk\0hclk";
		clocks = <0x02 0x47 0x02 0x44>;
		assigned-clocks = <0x02 0x45>;
		assigned-clock-parents = <0x02 0x05>;
		power-domains = <0x4f 0x26>;
		pinctrl-names = "default";
		pinctrl-0 = <0x11d>;
		#sound-dai-cells = <0x00>;
		status = "okay";
	};

	codec-digital@fe500000 {
		compatible = "rockchip,rk3588-codec-digital\0rockchip,codec-digital-v1";
		reg = <0x00 0xfe500000 0x00 0x1000>;
		clocks = <0x02 0x29 0x02 0x2f>;
		clock-names = "dac\0pclk";
		power-domains = <0x4f 0x26>;
		resets = <0x02 0x84>;
		reset-names = "reset";
		rockchip,grf = <0xb9>;
		rockchip,pwm-output-mode;
		pinctrl-names = "default";
		pinctrl-0 = <0x11e>;
		#sound-dai-cells = <0x00>;
		status = "disabled";
	};

	hwspinlock@fe5a0000 {
		compatible = "rockchip,hwspinlock";
		reg = <0x00 0xfe5a0000 0x00 0x100>;
		#hwlock-cells = <0x01>;
	};

	interrupt-controller@fe600000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <0x03>;
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		interrupt-controller;
		reg = <0x00 0xfe600000 0x00 0x10000 0x00 0xfe680000 0x00 0x100000>;
		interrupts = <0x01 0x09 0x04>;
		phandle = <0x01>;

		msi-controller@fe640000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <0x01>;
			reg = <0x00 0xfe640000 0x00 0x20000>;
			phandle = <0xe8>;
		};

		msi-controller@fe660000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <0x01>;
			reg = <0x00 0xfe660000 0x00 0x20000>;
		};
	};

	dma-controller@fea10000 {
		compatible = "arm,pl330\0arm,primecell";
		reg = <0x00 0xfea10000 0x00 0x4000>;
		interrupts = <0x00 0x56 0x04 0x00 0x57 0x04>;
		clocks = <0x02 0x78>;
		clock-names = "apb_pclk";
		#dma-cells = <0x01>;
		arm,pl330-periph-burst;
		phandle = <0x66>;
	};

	dma-controller@fea30000 {
		compatible = "arm,pl330\0arm,primecell";
		reg = <0x00 0xfea30000 0x00 0x4000>;
		interrupts = <0x00 0x58 0x04 0x00 0x59 0x04>;
		clocks = <0x02 0x79>;
		clock-names = "apb_pclk";
		#dma-cells = <0x01>;
		arm,pl330-periph-burst;
		phandle = <0xce>;
	};

	can@fea50000 {
		compatible = "rockchip,can-2.0";
		reg = <0x00 0xfea50000 0x00 0x1000>;
		interrupts = <0x00 0x155 0x04>;
		clocks = <0x02 0x70 0x02 0x6f>;
		clock-names = "baudclk\0apb_pclk";
		resets = <0x02 0xb9 0x02 0xb8>;
		reset-names = "can\0can-apb";
		pinctrl-names = "default";
		pinctrl-0 = <0x11f>;
		tx-fifo-depth = <0x01>;
		rx-fifo-depth = <0x06>;
		status = "disabled";
	};

	can@fea60000 {
		compatible = "rockchip,can-2.0";
		reg = <0x00 0xfea60000 0x00 0x1000>;
		interrupts = <0x00 0x156 0x04>;
		clocks = <0x02 0x72 0x02 0x71>;
		clock-names = "baudclk\0apb_pclk";
		resets = <0x02 0xbb 0x02 0xba>;
		reset-names = "can\0can-apb";
		pinctrl-names = "default";
		pinctrl-0 = <0x120>;
		tx-fifo-depth = <0x01>;
		rx-fifo-depth = <0x06>;
		status = "disabled";
	};

	can@fea70000 {
		compatible = "rockchip,can-2.0";
		reg = <0x00 0xfea70000 0x00 0x1000>;
		interrupts = <0x00 0x157 0x04>;
		clocks = <0x02 0x74 0x02 0x73>;
		clock-names = "baudclk\0apb_pclk";
		resets = <0x02 0xbd 0x02 0xbc>;
		reset-names = "can\0can-apb";
		pinctrl-names = "default";
		pinctrl-0 = <0x121>;
		tx-fifo-depth = <0x01>;
		rx-fifo-depth = <0x06>;
		status = "disabled";
	};

	decompress@fea80000 {
		compatible = "rockchip,hw-decompress";
		reg = <0x00 0xfea80000 0x00 0x1000>;
		interrupts = <0x00 0x55 0x04>;
		clocks = <0x02 0x75 0x02 0x77 0x02 0x76>;
		clock-names = "aclk\0dclk\0pclk";
		resets = <0x02 0x118>;
		reset-names = "dresetn";
		status = "disabled";
	};

	i2c@fea90000 {
		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
		reg = <0x00 0xfea90000 0x00 0x1000>;
		clocks = <0x02 0x8d 0x02 0x85>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x13e 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x122>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
	};

	i2c@feaa0000 {
		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
		reg = <0x00 0xfeaa0000 0x00 0x1000>;
		clocks = <0x02 0x8e 0x02 0x86>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x13f 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x123>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";

		rk8602@42 {
			compatible = "rockchip,rk8602";
			reg = <0x42>;
			vin-supply = <0x65>;
			regulator-compatible = "rk860x-reg";
			regulator-name = "vdd_npu_s0";
			regulator-min-microvolt = <0x86470>;
			regulator-max-microvolt = <0xe7ef0>;
			regulator-ramp-delay = <0x8fc>;
			rockchip,suspend-voltage-selector = <0x01>;
			regulator-boot-on;
			regulator-always-on;
			phandle = <0x9d>;

			regulator-state-mem {
				regulator-off-in-suspend;
			};
		};
	};

	i2c@feab0000 {
		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
		reg = <0x00 0xfeab0000 0x00 0x1000>;
		clocks = <0x02 0x8f 0x02 0x87>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x140 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x124>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	i2c@feac0000 {
		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
		reg = <0x00 0xfeac0000 0x00 0x1000>;
		clocks = <0x02 0x90 0x02 0x88>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x141 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x125>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";

		tinker_mcu@45 {
			compatible = "tinker_mcu";
			reg = <0x45>;
		};

		tinker_mcu_ili9881c@36 {
			compatible = "tinker_mcu_ili9881c";
			reg = <0x36>;
		};

		tinker_ft5406@38 {
			compatible = "tinker_ft5406";
			reg = <0x38>;
		};
	};

	i2c@fead0000 {
		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
		reg = <0x00 0xfead0000 0x00 0x1000>;
		clocks = <0x02 0x91 0x02 0x89>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x142 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x126>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	timer@feae0000 {
		compatible = "rockchip,rk3588-timer\0rockchip,rk3288-timer";
		reg = <0x00 0xfeae0000 0x00 0x20>;
		interrupts = <0x00 0x121 0x04>;
		clocks = <0x02 0x5c 0x02 0x5f>;
		clock-names = "pclk\0timer";
	};

	watchdog@feaf0000 {
		compatible = "snps,dw-wdt";
		reg = <0x00 0xfeaf0000 0x00 0x100>;
		clocks = <0x02 0x6c 0x02 0x6b>;
		clock-names = "tclk\0pclk";
		interrupts = <0x00 0x13b 0x04>;
		status = "disabled";
	};

	spi@feb00000 {
		compatible = "rockchip,rk3066-spi";
		reg = <0x00 0xfeb00000 0x00 0x1000>;
		interrupts = <0x00 0x146 0x04>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		clocks = <0x02 0xa3 0x02 0x9e>;
		clock-names = "spiclk\0apb_pclk";
		dmas = <0x66 0x0e 0x66 0x0f>;
		dma-names = "tx\0rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x127 0x128 0x129>;
		num-cs = <0x02>;
		status = "okay";
		max-freq = <0x2dc6c00>;

		spi_dev@0 {
			compatible = "rockchip,spidev";
			reg = <0x00>;
			spi-max-frequency = <0xb71b00>;
			spi-lsb-first;
		};

		spi_dev@1 {
			compatible = "rockchip,spidev";
			reg = <0x01>;
			spi-max-frequency = <0xb71b00>;
			spi-lsb-first;
		};
	};

	spi@feb10000 {
		compatible = "rockchip,rk3066-spi";
		reg = <0x00 0xfeb10000 0x00 0x1000>;
		interrupts = <0x00 0x147 0x04>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		clocks = <0x02 0xa4 0x02 0x9f>;
		clock-names = "spiclk\0apb_pclk";
		dmas = <0x66 0x10 0x66 0x11>;
		dma-names = "tx\0rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x12a 0x12b 0x12c>;
		num-cs = <0x02>;
		status = "disabled";
	};

	spi@feb20000 {
		compatible = "rockchip,rk3066-spi";
		reg = <0x00 0xfeb20000 0x00 0x1000>;
		interrupts = <0x00 0x148 0x04>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		clocks = <0x02 0xa5 0x02 0xa0>;
		clock-names = "spiclk\0apb_pclk";
		dmas = <0xce 0x0f 0xce 0x10>;
		dma-names = "tx\0rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x12d 0x12e>;
		num-cs = <0x01>;
		status = "okay";
		assigned-clocks = <0x02 0xa5>;
		assigned-clock-rates = <0xbebc200>;

		rk806single@0 {
			compatible = "rockchip,rk806";
			spi-max-frequency = <0xf4240>;
			reg = <0x00>;
			interrupt-parent = <0x12f>;
			interrupts = <0x07 0x08>;
			pinctrl-names = "default\0pmic-power-off";
			pinctrl-0 = <0x130 0x131 0x132 0x133>;
			pinctrl-1 = <0x134>;
			low_voltage_threshold = <0xbb8>;
			shutdown_voltage_threshold = <0xa8c>;
			shutdown_temperture_threshold = <0xa0>;
			hotdie_temperture_threshold = <0x73>;
			pmic-reset-func = <0x01>;
			vcc1-supply = <0x65>;
			vcc2-supply = <0x65>;
			vcc3-supply = <0x65>;
			vcc4-supply = <0x65>;
			vcc5-supply = <0x65>;
			vcc6-supply = <0x65>;
			vcc7-supply = <0x65>;
			vcc8-supply = <0x65>;
			vcc9-supply = <0x65>;
			vcc10-supply = <0x65>;
			vcc11-supply = <0x135>;
			vcc12-supply = <0x65>;
			vcc13-supply = <0x136>;
			vcc14-supply = <0x136>;
			vcca-supply = <0x65>;

			pwrkey {
				status = "okay";
			};

			pinctrl_rk806 {
				gpio-controller;
				#gpio-cells = <0x02>;

				rk806_dvs1_null {
					pins = "gpio_pwrctrl2";
					function = "pin_fun0";
					phandle = <0x131>;
				};

				rk806_dvs1_slp {
					pins = "gpio_pwrctrl1";
					function = "pin_fun1";
				};

				rk806_dvs1_pwrdn {
					pins = "gpio_pwrctrl1";
					function = "pin_fun2";
					phandle = <0x134>;
				};

				rk806_dvs1_rst {
					pins = "gpio_pwrctrl1";
					function = "pin_fun3";
				};

				rk806_dvs2_null {
					pins = "gpio_pwrctrl2";
					function = "pin_fun0";
					phandle = <0x132>;
				};

				rk806_dvs2_slp {
					pins = "gpio_pwrctrl2";
					function = "pin_fun1";
				};

				rk806_dvs2_pwrdn {
					pins = "gpio_pwrctrl2";
					function = "pin_fun2";
				};

				rk806_dvs2_rst {
					pins = "gpio_pwrctrl2";
					function = "pin_fun3";
				};

				rk806_dvs2_dvs {
					pins = "gpio_pwrctrl2";
					function = "pin_fun4";
				};

				rk806_dvs2_gpio {
					pins = "gpio_pwrctrl2";
					function = "pin_fun5";
				};

				rk806_dvs3_null {
					pins = "gpio_pwrctrl3";
					function = "pin_fun0";
					phandle = <0x133>;
				};

				rk806_dvs3_slp {
					pins = "gpio_pwrctrl3";
					function = "pin_fun1";
				};

				rk806_dvs3_pwrdn {
					pins = "gpio_pwrctrl3";
					function = "pin_fun2";
				};

				rk806_dvs3_rst {
					pins = "gpio_pwrctrl3";
					function = "pin_fun3";
				};

				rk806_dvs3_dvs {
					pins = "gpio_pwrctrl3";
					function = "pin_fun4";
				};

				rk806_dvs3_gpio {
					pins = "gpio_pwrctrl3";
					function = "pin_fun5";
				};
			};

			regulators {

				DCDC_REG1 {
					regulator-boot-on;
					regulator-min-microvolt = <0x86470>;
					regulator-max-microvolt = <0xe7ef0>;
					regulator-ramp-delay = <0x30d4>;
					regulator-name = "vdd_gpu_s0";
					regulator-enable-ramp-delay = <0x190>;
					phandle = <0x51>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				DCDC_REG2 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x86470>;
					regulator-max-microvolt = <0xe7ef0>;
					regulator-ramp-delay = <0x30d4>;
					regulator-name = "vdd_cpu_lit_s0";
					phandle = <0x1b>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				DCDC_REG3 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xa4cb8>;
					regulator-max-microvolt = <0xb71b0>;
					regulator-ramp-delay = <0x30d4>;
					regulator-name = "vdd_log_s0";

					regulator-state-mem {
						regulator-off-in-suspend;
						regulator-suspend-microvolt = <0xb71b0>;
					};
				};

				DCDC_REG4 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x86470>;
					regulator-max-microvolt = <0xe7ef0>;
					regulator-init-microvolt = <0xb71b0>;
					regulator-ramp-delay = <0x30d4>;
					regulator-name = "vdd_vdenc_s0";

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				DCDC_REG5 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xa4cb8>;
					regulator-max-microvolt = <0xdbba0>;
					regulator-ramp-delay = <0x30d4>;
					regulator-name = "vdd_ddr_s0";

					regulator-state-mem {
						regulator-off-in-suspend;
						regulator-suspend-microvolt = <0xcf850>;
					};
				};

				DCDC_REG6 {
					regulator-always-on;
					regulator-boot-on;
					regulator-name = "vdd2_ddr_s3";

					regulator-state-mem {
						regulator-on-in-suspend;
					};
				};

				DCDC_REG7 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1e8480>;
					regulator-max-microvolt = <0x1e8480>;
					regulator-name = "vdd_2v0_pldo_s3";
					phandle = <0x135>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x1e8480>;
					};
				};

				DCDC_REG8 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x325aa0>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-name = "vcc_3v3_s3";
					phandle = <0x189>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x325aa0>;
					};
				};

				DCDC_REG9 {
					regulator-always-on;
					regulator-boot-on;
					regulator-name = "vddq_ddr_s0";

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				DCDC_REG10 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					regulator-name = "vcc_1v8_s3";

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x1b7740>;
					};
				};

				PLDO_REG1 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					regulator-name = "avcc_1v8_s0";
					phandle = <0x183>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				PLDO_REG2 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					regulator-name = "vcc_1v8_s0";
					phandle = <0x152>;

					regulator-state-mem {
						regulator-off-in-suspend;
						regulator-suspend-microvolt = <0x1b7740>;
					};
				};

				PLDO_REG3 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x124f80>;
					regulator-max-microvolt = <0x124f80>;
					regulator-name = "avdd_1v2_s0";

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				PLDO_REG4 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x325aa0>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-name = "vcc_3v3_s0";
					phandle = <0x185>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				PLDO_REG5 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-name = "vccio_sd_s0";
					phandle = <0xf5>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				PLDO_REG6 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					regulator-name = "pldo6_s3";

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x1b7740>;
					};
				};

				NLDO_REG1 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xb71b0>;
					regulator-max-microvolt = <0xb71b0>;
					regulator-name = "vdd_0v75_s3";

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0xb71b0>;
					};
				};

				NLDO_REG2 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xcf850>;
					regulator-max-microvolt = <0xcf850>;
					regulator-name = "vdd_ddr_pll_s0";

					regulator-state-mem {
						regulator-off-in-suspend;
						regulator-suspend-microvolt = <0xcf850>;
					};
				};

				NLDO_REG3 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xcc77c>;
					regulator-max-microvolt = <0xcc77c>;
					regulator-name = "avdd_0v75_s0";

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				NLDO_REG4 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xcf850>;
					regulator-max-microvolt = <0xcf850>;
					regulator-name = "vdd_0v85_s0";
					phandle = <0x182>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				NLDO_REG5 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xb71b0>;
					regulator-max-microvolt = <0xb71b0>;
					regulator-name = "vdd_0v75_s0";

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};
			};
		};
	};

	spi@feb30000 {
		compatible = "rockchip,rk3066-spi";
		reg = <0x00 0xfeb30000 0x00 0x1000>;
		interrupts = <0x00 0x149 0x04>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		clocks = <0x02 0xa6 0x02 0xa1>;
		clock-names = "spiclk\0apb_pclk";
		dmas = <0xce 0x11 0xce 0x12>;
		dma-names = "tx\0rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x137 0x138 0x139>;
		num-cs = <0x02>;
		status = "disabled";
	};

	serial@feb40000 {
		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfeb40000 0x00 0x100>;
		interrupts = <0x00 0x14c 0x04>;
		clocks = <0x02 0xb7 0x02 0xab>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0x66 0x08 0x66 0x09>;
		pinctrl-names = "default";
		pinctrl-0 = <0x13a>;
		status = "disabled";
	};

	serial@feb50000 {
		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfeb50000 0x00 0x100>;
		interrupts = <0x00 0x14d 0x04>;
		clocks = <0x02 0xbb 0x02 0xac>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0x66 0x0a 0x66 0x0b>;
		pinctrl-names = "default";
		pinctrl-0 = <0x13b>;
		status = "okay";
	};

	serial@feb60000 {
		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfeb60000 0x00 0x100>;
		interrupts = <0x00 0x14e 0x04>;
		clocks = <0x02 0xbf 0x02 0xad>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0x66 0x0c 0x66 0x0d>;
		pinctrl-names = "default";
		pinctrl-0 = <0x13c>;
		status = "disabled";
	};

	serial@feb70000 {
		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfeb70000 0x00 0x100>;
		interrupts = <0x00 0x14f 0x04>;
		clocks = <0x02 0xc3 0x02 0xae>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0xce 0x09 0xce 0x0a>;
		pinctrl-names = "default";
		pinctrl-0 = <0x13d>;
		status = "disabled";
	};

	serial@feb80000 {
		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfeb80000 0x00 0x100>;
		interrupts = <0x00 0x150 0x04>;
		clocks = <0x02 0xc7 0x02 0xaf>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0xce 0x0b 0xce 0x0c>;
		pinctrl-names = "default";
		pinctrl-0 = <0x13e>;
		status = "disabled";
	};

	serial@feb90000 {
		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfeb90000 0x00 0x100>;
		interrupts = <0x00 0x151 0x04>;
		clocks = <0x02 0xcb 0x02 0xb0>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0xce 0x0d 0xce 0x0e>;
		pinctrl-names = "default";
		pinctrl-0 = <0x13f>;
		status = "okay";
	};

	serial@feba0000 {
		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfeba0000 0x00 0x100>;
		interrupts = <0x00 0x152 0x04>;
		clocks = <0x02 0xcf 0x02 0xb1>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0xcf 0x07 0xcf 0x08>;
		pinctrl-names = "default";
		pinctrl-0 = <0x140>;
		status = "disabled";
	};

	serial@febb0000 {
		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfebb0000 0x00 0x100>;
		interrupts = <0x00 0x153 0x04>;
		clocks = <0x02 0xd3 0x02 0xb2>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0xcf 0x09 0xcf 0x0a>;
		pinctrl-names = "default";
		pinctrl-0 = <0x141>;
		status = "disabled";
	};

	serial@febc0000 {
		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfebc0000 0x00 0x100>;
		interrupts = <0x00 0x154 0x04>;
		clocks = <0x02 0xd7 0x02 0xb3>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0xcf 0x0b 0xcf 0x0c>;
		pinctrl-names = "default";
		pinctrl-0 = <0x142 0x143>;
		status = "okay";
	};

	pwm@febd0000 {
		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfebd0000 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x144>;
		clocks = <0x02 0x54 0x02 0x53>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@febd0010 {
		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfebd0010 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x145>;
		clocks = <0x02 0x54 0x02 0x53>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@febd0020 {
		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfebd0020 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x146>;
		clocks = <0x02 0x54 0x02 0x53>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@febd0030 {
		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfebd0030 0x00 0x10>;
		interrupts = <0x00 0x15a 0x04 0x00 0x15b 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x147>;
		clocks = <0x02 0x54 0x02 0x53>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@febe0000 {
		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfebe0000 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x148>;
		clocks = <0x02 0x57 0x02 0x56>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@febe0010 {
		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfebe0010 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x149>;
		clocks = <0x02 0x57 0x02 0x56>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@febe0020 {
		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfebe0020 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x14a>;
		clocks = <0x02 0x57 0x02 0x56>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@febe0030 {
		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfebe0030 0x00 0x10>;
		interrupts = <0x00 0x15c 0x04 0x00 0x15d 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x14b>;
		clocks = <0x02 0x57 0x02 0x56>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@febf0000 {
		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfebf0000 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x14c>;
		clocks = <0x02 0x5a 0x02 0x59>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@febf0010 {
		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfebf0010 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x14d>;
		clocks = <0x02 0x5a 0x02 0x59>;
		clock-names = "pwm\0pclk";
		status = "okay";
		phandle = <0x176>;
	};

	pwm@febf0020 {
		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfebf0020 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x14e>;
		clocks = <0x02 0x5a 0x02 0x59>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@febf0030 {
		compatible = "rockchip,remotectl-pwm";
		reg = <0x00 0xfebf0030 0x00 0x10>;
		interrupts = <0x00 0x15e 0x04 0x00 0x15f 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "default";
		pinctrl-0 = <0x14f>;
		clocks = <0x02 0x5a 0x02 0x59>;
		clock-names = "pwm\0pclk";
		status = "disabled";
		remote_pwm_id = <0x03>;
		handle_cpu_id = <0x01>;
		remote_support_psci = <0x00>;

		ir_key1 {
			rockchip,usercode = <0x4040>;
			rockchip,key_table = <0xf2 0xe8 0xba 0x9e 0xf4 0x67 0xf1 0x6c 0xef 0x69 0xee 0x6a 0xbd 0x66 0xea 0x73 0xe3 0x72 0xe2 0xd9 0xb2 0x74 0xbc 0x71 0xec 0x8b 0xbf 0x190 0xe0 0x191 0xe1 0x192 0xe9 0xb7 0xe6 0xf8 0xe8 0xb9 0xe7 0xba 0xf0 0x184 0xbe 0x175>;
		};
	};

	tsadc@fec00000 {
		compatible = "rockchip,rk3588-tsadc";
		reg = <0x00 0xfec00000 0x00 0x400>;
		interrupts = <0x00 0x18d 0x04>;
		clocks = <0x02 0xaa 0x02 0xa9>;
		clock-names = "tsadc\0apb_pclk";
		assigned-clocks = <0x02 0xaa>;
		assigned-clock-rates = <0x1e8480>;
		resets = <0x02 0xc1 0x02 0xc0>;
		reset-names = "tsadc\0tsadc-apb";
		#thermal-sensor-cells = <0x01>;
		rockchip,hw-tshut-temp = <0x1d4c0>;
		rockchip,hw-tshut-mode = <0x00>;
		rockchip,hw-tshut-polarity = <0x00>;
		pinctrl-names = "gpio\0otpout";
		pinctrl-0 = <0x150>;
		pinctrl-1 = <0x151>;
		status = "okay";
		phandle = <0x4c>;
	};

	saradc@fec10000 {
		compatible = "rockchip,rk3588-saradc";
		reg = <0x00 0xfec10000 0x00 0x10000>;
		interrupts = <0x00 0x18e 0x04>;
		#io-channel-cells = <0x01>;
		clocks = <0x02 0x9d 0x02 0x9c>;
		clock-names = "saradc\0apb_pclk";
		resets = <0x02 0xbe>;
		reset-names = "saradc-apb";
		status = "okay";
		vref-supply = <0x152>;
		phandle = <0x175>;
	};

	mailbox@fec60000 {
		compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox";
		reg = <0x00 0xfec60000 0x00 0x200>;
		interrupts = <0x00 0x3d 0x04 0x00 0x3e 0x04 0x00 0x3f 0x04 0x00 0x40 0x04>;
		clocks = <0x02 0x4c>;
		clock-names = "pclk_mailbox";
		#mbox-cells = <0x01>;
		status = "disabled";
	};

	mailbox@fec70000 {
		compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox";
		reg = <0x00 0xfec70000 0x00 0x200>;
		interrupts = <0x00 0x45 0x04 0x00 0x46 0x04 0x00 0x47 0x04 0x00 0x48 0x04>;
		clocks = <0x02 0x4d>;
		clock-names = "pclk_mailbox";
		#mbox-cells = <0x01>;
		status = "disabled";
	};

	i2c@fec80000 {
		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
		reg = <0x00 0xfec80000 0x00 0x1000>;
		clocks = <0x02 0x92 0x02 0x8a>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x143 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x153>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";

		hym8563@51 {
			compatible = "haoyu,hym8563";
			reg = <0x51>;
			#clock-cells = <0x00>;
			clock-frequency = <0x8000>;
			clock-output-names = "hym8563";
			pinctrl-names = "default";
			pinctrl-0 = <0x154>;
			interrupt-parent = <0x12f>;
			interrupts = <0x08 0x08>;
			status = "okay";
			phandle = <0x17e>;
		};
	};

	i2c@fec90000 {
		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
		reg = <0x00 0xfec90000 0x00 0x1000>;
		clocks = <0x02 0x93 0x02 0x8b>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x144 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x155>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";

		es8316@10 {
			status = "okay";
			#sound-dai-cells = <0x00>;
			compatible = "everest,es8316";
			reg = <0x10>;
			clocks = <0x02 0x39>;
			clock-names = "mclk";
			assigned-clocks = <0x02 0x39>;
			assigned-clock-rates = <0xbb8000>;
			pinctrl-names = "default";
			pinctrl-0 = <0x156>;
			phandle = <0x17c>;
		};
	};

	i2c@feca0000 {
		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
		reg = <0x00 0xfeca0000 0x00 0x1000>;
		clocks = <0x02 0x94 0x02 0x8c>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x145 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x157>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";

		ov5647@36 {
			status = "okay";
			compatible = "ovti,ov5647";
			reg = <0x36>;
			clocks = <0x02 0xff>;
			clock-names = "xvclk";
			power-domains = <0x4f 0x1b>;
			pinctrl-names = "default";
			pinctrl-0 = <0x158>;
			avdd-supply = <0x159>;
			rockchip,camera-module-index = <0x01>;
			rockchip,camera-module-facing = "front";
			rockchip,camera-module-name = "THDS11073LarganCAM0";
			rockchip,camera-module-lens-name = "40122a1";

			port {

				endpoint {
					remote-endpoint = <0x15a>;
					data-lanes = <0x01 0x02>;
					phandle = <0x2d>;
				};
			};
		};

		imx477@1a {
			compatible = "sony,imx477";
			reg = <0x1a>;
			clocks = <0x02 0xff>;
			clock-names = "xvclk";
			power-domains = <0x4f 0x1b>;
			pinctrl-names = "default";
			pinctrl-0 = <0x158>;
			avdd-supply = <0x159>;
			rockchip,camera-module-index = <0x01>;
			rockchip,camera-module-facing = "front";
			rockchip,camera-module-name = "COOLPIIMXCAM0";
			rockchip,camera-module-lens-name = "IMX477";

			port {

				endpoint {
					remote-endpoint = <0x15b>;
					data-lanes = <0x01 0x02>;
					phandle = <0x2e>;
				};
			};
		};

		imx219@10 {
			compatible = "sony,imx219";
			status = "okay";
			reg = <0x10>;
			clocks = <0x02 0xff>;
			clock-names = "xvclk";
			pinctrl-names = "default";
			pinctrl-0 = <0x158>;
			power-domains = <0x4f 0x1b>;
			avdd-supply = <0x159>;
			rockchip,camera-module-index = <0x01>;
			rockchip,camera-module-facing = "front";
			rockchip,camera-module-name = "GEIR180089";
			rockchip,camera-module-lens-name = "LG500627G";

			port {

				endpoint {
					remote-endpoint = <0x15c>;
					data-lanes = <0x01 0x02>;
					clock-noncontinuous;
					link-frequencies = <0x00 0x1b2e0200>;
					phandle = <0x2f>;
				};
			};
		};
	};

	spi@fecb0000 {
		compatible = "rockchip,rk3066-spi";
		reg = <0x00 0xfecb0000 0x00 0x1000>;
		interrupts = <0x00 0x14a 0x04>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		clocks = <0x02 0xa7 0x02 0xa2>;
		clock-names = "spiclk\0apb_pclk";
		dmas = <0xcf 0x0d 0xcf 0x0e>;
		dma-names = "tx\0rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x15d 0x15e 0x15f>;
		num-cs = <0x02>;
		status = "disabled";
	};

	otp@fecc0000 {
		compatible = "rockchip,rk3588-otp";
		reg = <0x00 0xfecc0000 0x00 0x400>;
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		clocks = <0x02 0x96 0x02 0x95 0x02 0x97 0x02 0x99>;
		clock-names = "otpc\0apb\0arb\0phy";
		resets = <0x02 0x12a 0x02 0x129 0x02 0x12b>;
		reset-names = "otpc\0apb\0arb";

		cpu-code@2 {
			reg = <0x02 0x02>;
			phandle = <0x29>;
		};

		specification-serial-number@6 {
			reg = <0x06 0x01>;
			bits = <0x00 0x05>;
			phandle = <0x20>;
		};

		id@7 {
			reg = <0x07 0x10>;
			phandle = <0x27>;
		};

		cpu-version@1c {
			reg = <0x1c 0x01>;
			bits = <0x03 0x03>;
			phandle = <0x28>;
		};

		cpub0-leakage@17 {
			reg = <0x17 0x01>;
			phandle = <0x23>;
		};

		cpub1-leakage@18 {
			reg = <0x18 0x01>;
			phandle = <0x25>;
		};

		cpul-leakage@19 {
			reg = <0x19 0x01>;
			phandle = <0x1f>;
		};

		log-leakage@1a {
			reg = <0x1a 0x01>;
			phandle = <0x3c>;
		};

		gpu-leakage@1b {
			reg = <0x1b 0x01>;
			phandle = <0x52>;
		};

		npu-leakage@28 {
			reg = <0x28 0x01>;
			phandle = <0x9e>;
		};

		codec-leakage@29 {
			reg = <0x29 0x01>;
		};
	};

	mailbox@fece0000 {
		compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox";
		reg = <0x00 0xfece0000 0x00 0x200>;
		interrupts = <0x00 0x4d 0x04 0x00 0x4e 0x04 0x00 0x4f 0x04 0x00 0x50 0x04>;
		clocks = <0x02 0x4e>;
		clock-names = "pclk_mailbox";
		#mbox-cells = <0x01>;
		status = "disabled";
	};

	dma-controller@fed10000 {
		compatible = "arm,pl330\0arm,primecell";
		reg = <0x00 0xfed10000 0x00 0x4000>;
		interrupts = <0x00 0x5a 0x04 0x00 0x5b 0x04>;
		clocks = <0x02 0x7a>;
		clock-names = "apb_pclk";
		#dma-cells = <0x01>;
		arm,pl330-periph-burst;
		phandle = <0xcf>;
	};

	phy@fed60000 {
		compatible = "rockchip,rk3588-hdptx-phy";
		reg = <0x00 0xfed60000 0x00 0x2000>;
		clocks = <0x02 0x2b5 0x02 0x267>;
		clock-names = "ref\0apb";
		resets = <0x02 0x485 0x02 0xc003b 0x02 0xc003c 0x02 0xc003d>;
		reset-names = "apb\0init\0cmn\0lane";
		rockchip,grf = <0x160>;
		#phy-cells = <0x00>;
		status = "disabled";
		phandle = <0xe3>;
	};

	hdmiphy@fed60000 {
		compatible = "rockchip,rk3588-hdptx-phy-hdmi";
		reg = <0x00 0xfed60000 0x00 0x2000>;
		clocks = <0x02 0x2b5 0x02 0x267>;
		clock-names = "ref\0apb";
		resets = <0x02 0x48e 0x02 0x485 0x02 0xc003b 0x02 0xc003c 0x02 0xc003d 0x02 0x48c 0x02 0x48d>;
		reset-names = "phy\0apb\0init\0cmn\0lane\0ropll\0lcpll";
		rockchip,grf = <0x160>;
		#phy-cells = <0x00>;
		status = "okay";
		phandle = <0xdf>;

		clk-port {
			#clock-cells = <0x00>;
			status = "okay";
			phandle = <0x32>;
		};
	};

	phy@fed80000 {
		compatible = "rockchip,rk3588-usbdp-phy";
		reg = <0x00 0xfed80000 0x00 0x10000>;
		rockchip,u2phy-grf = <0x161>;
		rockchip,usb-grf = <0x60>;
		rockchip,usbdpphy-grf = <0x162>;
		rockchip,vo-grf = <0xd6>;
		clocks = <0x02 0x2b6 0x02 0x27f 0x02 0x269 0x163>;
		clock-names = "refclk\0immortal\0pclk\0utmi";
		resets = <0x02 0x28 0x02 0x29 0x02 0x2a 0x02 0x2b 0x02 0x482>;
		reset-names = "init\0cmn\0lane\0pcs_apb\0pma_apb";
		status = "okay";
		rockchip,dp-lane-mux = <0x00 0x01>;

		dp-port {
			#phy-cells = <0x00>;
			status = "okay";
			phandle = <0xd7>;
		};

		u3-port {
			#phy-cells = <0x00>;
			status = "okay";
			phandle = <0x55>;
		};
	};

	phy@feda0000 {
		compatible = "rockchip,rk3588-mipi-dcphy";
		reg = <0x00 0xfeda0000 0x00 0x10000>;
		rockchip,grf = <0x164>;
		clocks = <0x02 0x108 0x02 0x2b6>;
		clock-names = "pclk\0ref";
		resets = <0x02 0xc0043 0x02 0x3e 0x02 0x3f 0x02 0xc0044>;
		reset-names = "m_phy\0apb\0grf\0s_phy";
		#phy-cells = <0x00>;
		status = "disabled";
		phandle = <0x2a>;
	};

	phy@fedb0000 {
		compatible = "rockchip,rk3588-mipi-dcphy";
		reg = <0x00 0xfedb0000 0x00 0x10000>;
		rockchip,grf = <0x165>;
		clocks = <0x02 0x109 0x02 0x2b6>;
		clock-names = "pclk\0ref";
		resets = <0x02 0xc0045 0x02 0x43 0x02 0x44 0x02 0xc0046>;
		reset-names = "m_phy\0apb\0grf\0s_phy";
		#phy-cells = <0x00>;
		status = "disabled";
		phandle = <0x2b>;
	};

	csi2-dphy0-hw@fedc0000 {
		compatible = "rockchip,rk3588-csi2-dphy-hw";
		reg = <0x00 0xfedc0000 0x00 0x8000>;
		clocks = <0x02 0x10c>;
		clock-names = "pclk";
		resets = <0x02 0x17 0x02 0x16>;
		reset-names = "srst_csiphy0\0srst_p_csiphy0";
		rockchip,grf = <0x166>;
		rockchip,sys_grf = <0xb9>;
		status = "okay";
		phandle = <0x2c>;
	};

	phy@fee00000 {
		compatible = "rockchip,rk3588-naneng-combphy";
		reg = <0x00 0xfee00000 0x00 0x100>;
		#phy-cells = <0x01>;
		clocks = <0x02 0x2bd 0x02 0x185 0x02 0x166>;
		clock-names = "refclk\0apbclk\0phpclk";
		assigned-clocks = <0x02 0x2bd>;
		assigned-clock-rates = <0x5f5e100>;
		resets = <0x02 0x20005 0x02 0x4d6>;
		reset-names = "combphy-apb\0combphy";
		rockchip,pipe-grf = <0x63>;
		rockchip,pipe-phy-grf = <0x167>;
		status = "okay";
		phandle = <0xea>;
	};

	phy@fee20000 {
		compatible = "rockchip,rk3588-naneng-combphy";
		reg = <0x00 0xfee20000 0x00 0x100>;
		#phy-cells = <0x01>;
		clocks = <0x02 0x2bf 0x02 0x187 0x02 0x166>;
		clock-names = "refclk\0apbclk\0phpclk";
		assigned-clocks = <0x02 0x2bf>;
		assigned-clock-rates = <0x5f5e100>;
		resets = <0x02 0x20007 0x02 0x4d8>;
		reset-names = "combphy-apb\0combphy";
		rockchip,pipe-grf = <0x63>;
		rockchip,pipe-phy-grf = <0x168>;
		rockchip,pcie1ln-sel-bits = <0x100 0x01 0x01 0x00>;
		status = "okay";
		phandle = <0x5c>;
	};

	sram@ff001000 {
		compatible = "mmio-sram";
		reg = <0x00 0xff001000 0x00 0xef000>;
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		ranges = <0x00 0x00 0xff001000 0xef000>;

		rkvdec-sram@0 {
			reg = <0x00 0x78000>;
			phandle = <0xb0>;
		};

		rkvdec-sram@78000 {
			reg = <0x78000 0x77000>;
			phandle = <0xb2>;
		};
	};

	pinctrl {
		compatible = "rockchip,rk3588-pinctrl";
		rockchip,grf = <0x169>;
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		phandle = <0x16a>;

		gpio@fd8a0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xfd8a0000 0x00 0x100>;
			interrupts = <0x00 0x115 0x04>;
			clocks = <0x02 0x284 0x02 0x285>;
			gpio-controller;
			#gpio-cells = <0x02>;
			gpio-ranges = <0x16a 0x00 0x00 0x20>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0x12f>;
		};

		gpio@fec20000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xfec20000 0x00 0x100>;
			interrupts = <0x00 0x116 0x04>;
			clocks = <0x02 0x7d 0x02 0x7e>;
			gpio-controller;
			#gpio-cells = <0x02>;
			gpio-ranges = <0x16a 0x00 0x20 0x20>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0x188>;
		};

		gpio@fec30000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xfec30000 0x00 0x100>;
			interrupts = <0x00 0x117 0x04>;
			clocks = <0x02 0x7f 0x02 0x80>;
			gpio-controller;
			#gpio-cells = <0x02>;
			gpio-ranges = <0x16a 0x00 0x40 0x20>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
		};

		gpio@fec40000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xfec40000 0x00 0x100>;
			interrupts = <0x00 0x118 0x04>;
			clocks = <0x02 0x81 0x02 0x82>;
			gpio-controller;
			#gpio-cells = <0x02>;
			gpio-ranges = <0x16a 0x00 0x60 0x20>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0xeb>;
		};

		gpio@fec50000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xfec50000 0x00 0x100>;
			interrupts = <0x00 0x119 0x04>;
			clocks = <0x02 0x83 0x02 0x84>;
			gpio-controller;
			#gpio-cells = <0x02>;
			gpio-ranges = <0x16a 0x00 0x80 0x20>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0xe0>;
		};

		pcfg-pull-up {
			bias-pull-up;
			phandle = <0x170>;
		};

		pcfg-pull-down {
			bias-pull-down;
			phandle = <0x174>;
		};

		pcfg-pull-none {
			bias-disable;
			phandle = <0x16b>;
		};

		pcfg-pull-none-drv-level-2 {
			bias-disable;
			drive-strength = <0x02>;
			phandle = <0x173>;
		};

		pcfg-pull-up-drv-level-1 {
			bias-pull-up;
			drive-strength = <0x01>;
			phandle = <0x172>;
		};

		pcfg-pull-up-drv-level-2 {
			bias-pull-up;
			drive-strength = <0x02>;
			phandle = <0x16c>;
		};

		pcfg-pull-up-drv-level-6 {
			bias-pull-up;
			drive-strength = <0x06>;
			phandle = <0x171>;
		};

		pcfg-pull-none-smt {
			bias-disable;
			input-schmitt-enable;
			phandle = <0x16f>;
		};

		pcfg-pull-none-drv-level-1-smt {
			bias-disable;
			drive-strength = <0x01>;
			input-schmitt-enable;
			phandle = <0x16e>;
		};

		pcfg-pull-none-drv-level-5-smt {
			bias-disable;
			drive-strength = <0x05>;
			input-schmitt-enable;
			phandle = <0x16d>;
		};

		auddsm {

			auddsm-pins {
				rockchip,pins = <0x03 0x01 0x04 0x16b 0x03 0x02 0x04 0x16b 0x03 0x03 0x04 0x16b 0x03 0x04 0x04 0x16b>;
				phandle = <0x11e>;
			};
		};

		bt1120 {

			bt1120-pins {
				rockchip,pins = <0x04 0x08 0x02 0x16b 0x04 0x00 0x02 0x16b 0x04 0x01 0x02 0x16b 0x04 0x02 0x02 0x16b 0x04 0x03 0x02 0x16b 0x04 0x04 0x02 0x16b 0x04 0x05 0x02 0x16b 0x04 0x06 0x02 0x16b 0x04 0x07 0x02 0x16b 0x04 0x0a 0x02 0x16b 0x04 0x0b 0x02 0x16b 0x04 0x0c 0x02 0x16b 0x04 0x0d 0x02 0x16b 0x04 0x0e 0x02 0x16b 0x04 0x0f 0x02 0x16b 0x04 0x10 0x02 0x16b 0x04 0x11 0x02 0x16b>;
				phandle = <0x5d>;
			};
		};

		can0 {

			can0m0-pins {
				rockchip,pins = <0x00 0x10 0x0b 0x16b 0x00 0x0f 0x0b 0x16b>;
				phandle = <0x11f>;
			};
		};

		can1 {

			can1m1-pins {
				rockchip,pins = <0x04 0x0a 0x0c 0x16b 0x04 0x0b 0x0c 0x16b>;
				phandle = <0x120>;
			};
		};

		can2 {

			can2m0-pins {
				rockchip,pins = <0x03 0x14 0x09 0x16b 0x03 0x15 0x09 0x16b>;
				phandle = <0x121>;
			};
		};

		dp0 {

			dp0m0-pins {
				rockchip,pins = <0x04 0x0c 0x05 0x16b>;
				phandle = <0xd8>;
			};
		};

		hdmi {

			hdmim0-tx0-cec {
				rockchip,pins = <0x04 0x11 0x05 0x16b>;
				phandle = <0xdb>;
			};

			hdmim0-tx0-hpd {
				rockchip,pins = <0x01 0x05 0x05 0x16b>;
				phandle = <0xdc>;
			};

			hdmim0-tx0-scl {
				rockchip,pins = <0x04 0x0f 0x05 0x16d>;
				phandle = <0xdd>;
			};

			hdmim0-tx0-sda {
				rockchip,pins = <0x04 0x10 0x05 0x16e>;
				phandle = <0xde>;
			};
		};

		i2c0 {

			i2c0m2-xfer {
				rockchip,pins = <0x00 0x19 0x03 0x16f 0x00 0x1a 0x03 0x16f>;
				phandle = <0x64>;
			};
		};

		i2c1 {

			i2c1m2-xfer {
				rockchip,pins = <0x00 0x1c 0x09 0x16f 0x00 0x1d 0x09 0x16f>;
				phandle = <0x122>;
			};
		};

		i2c2 {

			i2c2m0-xfer {
				rockchip,pins = <0x00 0x0f 0x09 0x16f 0x00 0x10 0x09 0x16f>;
				phandle = <0x123>;
			};
		};

		i2c3 {

			i2c3m0-xfer {
				rockchip,pins = <0x01 0x11 0x09 0x16f 0x01 0x10 0x09 0x16f>;
				phandle = <0x124>;
			};
		};

		i2c4 {

			i2c4m3-xfer {
				rockchip,pins = <0x01 0x03 0x09 0x16f 0x01 0x02 0x09 0x16f>;
				phandle = <0x125>;
			};
		};

		i2c5 {

			i2c5m0-xfer {
				rockchip,pins = <0x03 0x17 0x09 0x16f 0x03 0x18 0x09 0x16f>;
				phandle = <0x126>;
			};
		};

		i2c6 {

			i2c6m3-xfer {
				rockchip,pins = <0x04 0x09 0x09 0x16f 0x04 0x08 0x09 0x16f>;
				phandle = <0x153>;
			};
		};

		i2c7 {

			i2c7m0-xfer {
				rockchip,pins = <0x01 0x18 0x09 0x16f 0x01 0x19 0x09 0x16f>;
				phandle = <0x155>;
			};
		};

		i2c8 {

			i2c8m2-xfer {
				rockchip,pins = <0x01 0x1e 0x09 0x16f 0x01 0x1f 0x09 0x16f>;
				phandle = <0x157>;
			};
		};

		i2s0 {

			i2s0-lrck {
				rockchip,pins = <0x01 0x15 0x01 0x16b>;
				phandle = <0xfa>;
			};

			i2s0-mclk {
				rockchip,pins = <0x01 0x12 0x01 0x16b>;
				phandle = <0x156>;
			};

			i2s0-sclk {
				rockchip,pins = <0x01 0x13 0x01 0x16b>;
				phandle = <0xfb>;
			};

			i2s0-sdi0 {
				rockchip,pins = <0x01 0x1c 0x02 0x16b>;
				phandle = <0xfc>;
			};

			i2s0-sdo0 {
				rockchip,pins = <0x01 0x17 0x01 0x16b>;
				phandle = <0xfd>;
			};
		};

		i2s1 {

			i2s1m0-lrck {
				rockchip,pins = <0x04 0x02 0x03 0x16b>;
				phandle = <0xfe>;
			};

			i2s1m0-sclk {
				rockchip,pins = <0x04 0x01 0x03 0x16b>;
				phandle = <0xff>;
			};

			i2s1m0-sdi0 {
				rockchip,pins = <0x04 0x05 0x03 0x16b>;
				phandle = <0x100>;
			};

			i2s1m0-sdi1 {
				rockchip,pins = <0x04 0x06 0x03 0x16b>;
				phandle = <0x101>;
			};

			i2s1m0-sdi2 {
				rockchip,pins = <0x04 0x07 0x03 0x16b>;
				phandle = <0x102>;
			};

			i2s1m0-sdi3 {
				rockchip,pins = <0x04 0x08 0x03 0x16b>;
				phandle = <0x103>;
			};

			i2s1m0-sdo0 {
				rockchip,pins = <0x04 0x09 0x03 0x16b>;
				phandle = <0x104>;
			};

			i2s1m0-sdo1 {
				rockchip,pins = <0x04 0x0a 0x03 0x16b>;
				phandle = <0x105>;
			};

			i2s1m0-sdo2 {
				rockchip,pins = <0x04 0x0b 0x03 0x16b>;
				phandle = <0x106>;
			};

			i2s1m0-sdo3 {
				rockchip,pins = <0x04 0x0c 0x03 0x16b>;
				phandle = <0x107>;
			};
		};

		i2s2 {

			i2s2m1-lrck {
				rockchip,pins = <0x03 0x0e 0x03 0x16b>;
				phandle = <0x108>;
			};

			i2s2m1-sclk {
				rockchip,pins = <0x03 0x0d 0x03 0x16b>;
				phandle = <0x109>;
			};

			i2s2m1-sdi {
				rockchip,pins = <0x03 0x0a 0x03 0x16b>;
				phandle = <0x10a>;
			};

			i2s2m1-sdo {
				rockchip,pins = <0x03 0x0b 0x03 0x16b>;
				phandle = <0x10b>;
			};
		};

		i2s3 {

			i2s3-lrck {
				rockchip,pins = <0x03 0x02 0x03 0x16b>;
				phandle = <0x10c>;
			};

			i2s3-sclk {
				rockchip,pins = <0x03 0x01 0x03 0x16b>;
				phandle = <0x10d>;
			};

			i2s3-sdi {
				rockchip,pins = <0x03 0x04 0x03 0x16b>;
				phandle = <0x10e>;
			};

			i2s3-sdo {
				rockchip,pins = <0x03 0x03 0x03 0x16b>;
				phandle = <0x10f>;
			};
		};

		pdm0 {

			pdm0m0-clk {
				rockchip,pins = <0x01 0x16 0x03 0x16b>;
				phandle = <0x110>;
			};

			pdm0m0-clk1 {
				rockchip,pins = <0x01 0x14 0x03 0x16b>;
				phandle = <0x111>;
			};

			pdm0m0-sdi0 {
				rockchip,pins = <0x01 0x1d 0x03 0x16b>;
				phandle = <0x112>;
			};

			pdm0m0-sdi1 {
				rockchip,pins = <0x01 0x19 0x03 0x16b>;
				phandle = <0x113>;
			};

			pdm0m0-sdi2 {
				rockchip,pins = <0x01 0x1a 0x03 0x16b>;
				phandle = <0x114>;
			};

			pdm0m0-sdi3 {
				rockchip,pins = <0x01 0x1b 0x03 0x16b>;
				phandle = <0x115>;
			};
		};

		pdm1 {

			pdm1m0-clk {
				rockchip,pins = <0x04 0x1d 0x02 0x16b>;
				phandle = <0x116>;
			};

			pdm1m0-clk1 {
				rockchip,pins = <0x04 0x1c 0x02 0x16b>;
				phandle = <0x117>;
			};

			pdm1m0-sdi0 {
				rockchip,pins = <0x04 0x1b 0x02 0x16b>;
				phandle = <0x118>;
			};

			pdm1m0-sdi1 {
				rockchip,pins = <0x04 0x1a 0x02 0x16b>;
				phandle = <0x119>;
			};

			pdm1m0-sdi2 {
				rockchip,pins = <0x04 0x19 0x02 0x16b>;
				phandle = <0x11a>;
			};

			pdm1m0-sdi3 {
				rockchip,pins = <0x04 0x18 0x02 0x16b>;
				phandle = <0x11b>;
			};
		};

		pmic {

			pmic-pins {
				rockchip,pins = <0x00 0x07 0x00 0x170 0x00 0x02 0x01 0x16b 0x00 0x03 0x01 0x16b 0x00 0x11 0x01 0x16b 0x00 0x12 0x01 0x16b 0x00 0x13 0x01 0x16b 0x00 0x1e 0x01 0x16b>;
				phandle = <0x130>;
			};
		};

		pwm0 {

			pwm0m0-pins {
				rockchip,pins = <0x00 0x0f 0x03 0x16b>;
				phandle = <0x68>;
			};
		};

		pwm1 {

			pwm1m0-pins {
				rockchip,pins = <0x00 0x10 0x03 0x16b>;
				phandle = <0x69>;
			};
		};

		pwm2 {

			pwm2m1-pins {
				rockchip,pins = <0x03 0x09 0x0b 0x16b>;
				phandle = <0x6a>;
			};
		};

		pwm3 {

			pwm3m0-pins {
				rockchip,pins = <0x00 0x1c 0x03 0x16b>;
				phandle = <0x6b>;
			};
		};

		pwm4 {

			pwm4m0-pins {
				rockchip,pins = <0x00 0x15 0x0b 0x16b>;
				phandle = <0x144>;
			};
		};

		pwm5 {

			pwm5m0-pins {
				rockchip,pins = <0x00 0x09 0x03 0x16b>;
				phandle = <0x145>;
			};
		};

		pwm6 {

			pwm6m0-pins {
				rockchip,pins = <0x00 0x17 0x0b 0x16b>;
				phandle = <0x146>;
			};
		};

		pwm7 {

			pwm7m0-pins {
				rockchip,pins = <0x00 0x18 0x0b 0x16b>;
				phandle = <0x147>;
			};
		};

		pwm8 {

			pwm8m0-pins {
				rockchip,pins = <0x03 0x07 0x0b 0x16b>;
				phandle = <0x148>;
			};
		};

		pwm9 {

			pwm9m0-pins {
				rockchip,pins = <0x03 0x08 0x0b 0x16b>;
				phandle = <0x149>;
			};
		};

		pwm10 {

			pwm10m0-pins {
				rockchip,pins = <0x03 0x00 0x0b 0x16b>;
				phandle = <0x14a>;
			};
		};

		pwm11 {

			pwm11m1-pins {
				rockchip,pins = <0x04 0x0c 0x0b 0x16b>;
				phandle = <0x14b>;
			};
		};

		pwm12 {

			pwm12m0-pins {
				rockchip,pins = <0x03 0x0d 0x0b 0x16b>;
				phandle = <0x14c>;
			};
		};

		pwm13 {

			pwm13m2-pins {
				rockchip,pins = <0x01 0x0f 0x0b 0x16b>;
				phandle = <0x14d>;
			};
		};

		pwm14 {

			pwm14m0-pins {
				rockchip,pins = <0x03 0x12 0x0b 0x16b>;
				phandle = <0x14e>;
			};
		};

		pwm15 {

			pwm15m0-pins {
				rockchip,pins = <0x03 0x13 0x0b 0x16b>;
				phandle = <0x14f>;
			};
		};

		sdio {

			sdiom1-pins {
				rockchip,pins = <0x03 0x05 0x02 0x16b 0x03 0x04 0x02 0x170 0x03 0x00 0x02 0x170 0x03 0x01 0x02 0x170 0x03 0x02 0x02 0x170 0x03 0x03 0x02 0x170>;
				phandle = <0xf6>;
			};
		};

		sdmmc {

			sdmmc-bus4 {
				rockchip,pins = <0x04 0x18 0x01 0x16c 0x04 0x19 0x01 0x16c 0x04 0x1a 0x01 0x16c 0x04 0x1b 0x01 0x16c>;
				phandle = <0xf3>;
			};

			sdmmc-clk {
				rockchip,pins = <0x04 0x1d 0x01 0x16c>;
				phandle = <0xf0>;
			};

			sdmmc-cmd {
				rockchip,pins = <0x04 0x1c 0x01 0x16c>;
				phandle = <0xf1>;
			};

			sdmmc-det {
				rockchip,pins = <0x00 0x04 0x01 0x170>;
				phandle = <0xf2>;
			};
		};

		spdif0 {

			spdif0m0-tx {
				rockchip,pins = <0x01 0x0e 0x03 0x16b>;
				phandle = <0x11c>;
			};
		};

		spdif1 {

			spdif1m0-tx {
				rockchip,pins = <0x01 0x0f 0x03 0x16b>;
				phandle = <0x11d>;
			};
		};

		spi0 {

			spi0m2-pins {
				rockchip,pins = <0x01 0x0b 0x08 0x171 0x01 0x09 0x08 0x171 0x01 0x0a 0x08 0x171>;
				phandle = <0x129>;
			};

			spi0m2-cs0 {
				rockchip,pins = <0x01 0x0c 0x08 0x171>;
				phandle = <0x127>;
			};

			spi0m2-cs1 {
				rockchip,pins = <0x01 0x0d 0x08 0x171>;
				phandle = <0x128>;
			};
		};

		spi1 {

			spi1m1-pins {
				rockchip,pins = <0x03 0x11 0x08 0x171 0x03 0x10 0x08 0x171 0x03 0x0f 0x08 0x171>;
				phandle = <0x12c>;
			};

			spi1m1-cs0 {
				rockchip,pins = <0x03 0x12 0x08 0x171>;
				phandle = <0x12a>;
			};

			spi1m1-cs1 {
				rockchip,pins = <0x03 0x13 0x08 0x171>;
				phandle = <0x12b>;
			};
		};

		spi2 {

			spi2m2-pins {
				rockchip,pins = <0x00 0x05 0x01 0x172 0x00 0x0b 0x01 0x172 0x00 0x06 0x01 0x172>;
				phandle = <0x12e>;
			};

			spi2m2-cs0 {
				rockchip,pins = <0x00 0x09 0x01 0x172>;
				phandle = <0x12d>;
			};
		};

		spi3 {

			spi3m1-pins {
				rockchip,pins = <0x04 0x0f 0x08 0x171 0x04 0x0d 0x08 0x171 0x04 0x0e 0x08 0x171>;
				phandle = <0x139>;
			};

			spi3m1-cs0 {
				rockchip,pins = <0x04 0x10 0x08 0x171>;
				phandle = <0x137>;
			};

			spi3m1-cs1 {
				rockchip,pins = <0x04 0x11 0x08 0x171>;
				phandle = <0x138>;
			};
		};

		spi4 {

			spi4m0-pins {
				rockchip,pins = <0x01 0x12 0x08 0x171 0x01 0x10 0x08 0x171 0x01 0x11 0x08 0x171>;
				phandle = <0x15f>;
			};

			spi4m0-cs0 {
				rockchip,pins = <0x01 0x13 0x08 0x171>;
				phandle = <0x15d>;
			};

			spi4m0-cs1 {
				rockchip,pins = <0x01 0x14 0x08 0x171>;
				phandle = <0x15e>;
			};
		};

		tsadc {

			tsadc-shut {
				rockchip,pins = <0x00 0x01 0x02 0x16b>;
				phandle = <0x151>;
			};
		};

		uart0 {

			uart0m1-xfer {
				rockchip,pins = <0x00 0x08 0x04 0x170 0x00 0x09 0x04 0x170>;
				phandle = <0x67>;
			};
		};

		uart1 {

			uart1m1-xfer {
				rockchip,pins = <0x01 0x0f 0x0a 0x170 0x01 0x0e 0x0a 0x170>;
				phandle = <0x13a>;
			};
		};

		uart2 {

			uart2m0-xfer {
				rockchip,pins = <0x00 0x0e 0x0a 0x170 0x00 0x0d 0x0a 0x170>;
				phandle = <0x13b>;
			};
		};

		uart3 {

			uart3m1-xfer {
				rockchip,pins = <0x03 0x0e 0x0a 0x170 0x03 0x0d 0x0a 0x170>;
				phandle = <0x13c>;
			};
		};

		uart4 {

			uart4m1-xfer {
				rockchip,pins = <0x03 0x18 0x0a 0x170 0x03 0x19 0x0a 0x170>;
				phandle = <0x13d>;
			};
		};

		uart5 {

			uart5m1-xfer {
				rockchip,pins = <0x03 0x15 0x0a 0x170 0x03 0x14 0x0a 0x170>;
				phandle = <0x13e>;
			};
		};

		uart6 {

			uart6m1-xfer {
				rockchip,pins = <0x01 0x00 0x0a 0x170 0x01 0x01 0x0a 0x170>;
				phandle = <0x13f>;
			};
		};

		uart7 {

			uart7m1-xfer {
				rockchip,pins = <0x03 0x11 0x0a 0x170 0x03 0x10 0x0a 0x170>;
				phandle = <0x140>;
			};
		};

		uart8 {

			uart8m1-xfer {
				rockchip,pins = <0x03 0x03 0x0a 0x170 0x03 0x02 0x0a 0x170>;
				phandle = <0x141>;
			};
		};

		uart9 {

			uart9m2-xfer {
				rockchip,pins = <0x03 0x1c 0x0a 0x170 0x03 0x1d 0x0a 0x170>;
				phandle = <0x142>;
			};

			uart9m2-ctsn {
				rockchip,pins = <0x03 0x1b 0x0a 0x16b>;
				phandle = <0x143>;
			};

			uart9m2-rtsn {
				rockchip,pins = <0x03 0x1a 0x0a 0x16b>;
				phandle = <0x18b>;
			};
		};

		gpio-func {

			tsadc-gpio-func {
				rockchip,pins = <0x00 0x01 0x00 0x16b>;
				phandle = <0x150>;
			};
		};

		hym8563 {

			hym8563-int {
				rockchip,pins = <0x00 0x08 0x00 0x170>;
				phandle = <0x154>;
			};
		};

		rtl8111 {

			rtl8111-isolate {
				rockchip,pins = <0x01 0x04 0x00 0x170>;
				phandle = <0xec>;
			};
		};

		cam {

			cam-clkout0 {
				rockchip,pins = <0x01 0x0e 0x01 0x16b>;
				phandle = <0x158>;
			};

			cam-en {
				rockchip,pins = <0x01 0x06 0x01 0x16b>;
				phandle = <0x18a>;
			};
		};

		led {

			gpio-leds {
				rockchip,pins = <0x00 0x14 0x00 0x174 0x00 0x18 0x00 0x174>;
				phandle = <0x17d>;
			};
		};

		usb {

			vcc5v0-host-en {
				rockchip,pins = <0x03 0x10 0x00 0x16b 0x04 0x0d 0x00 0x170>;
				phandle = <0x186>;
			};

			vcc5v0-u3host-en {
				rockchip,pins = <0x03 0x11 0x00 0x16b>;
				phandle = <0x187>;
			};
		};

		sdio-pwrseq {

			wifi-enable-h {
				rockchip,pins = <0x00 0x17 0x00 0x170>;
				phandle = <0x17f>;
			};
		};

		wireless-bluetooth {

			uart9-gpios {
				rockchip,pins = <0x03 0x1a 0x00 0x16b>;
				phandle = <0x18f>;
			};

			bt-reset-gpio {
				rockchip,pins = <0x00 0x1b 0x00 0x16b>;
				phandle = <0x18c>;
			};

			bt-wake-gpio {
				rockchip,pins = <0x00 0x16 0x00 0x16b>;
				phandle = <0x18d>;
			};

			bt-wake-host-irq {
				rockchip,pins = <0x00 0x15 0x00 0x174>;
				phandle = <0x18e>;
			};
		};

		wireless-wlan {

			wifi-host-wake-irq {
				rockchip,pins = <0x00 0x00 0x00 0x174>;
				phandle = <0x190>;
			};

			wifi-poweren-gpio {
				rockchip,pins = <0x01 0x1b 0x00 0x170>;
				phandle = <0xf7>;
			};
		};
	};

	cspmu@fd10c000 {
		compatible = "rockchip,cspmu";
		reg = <0x00 0xfd10c000 0x00 0x1000 0x00 0xfd10d000 0x00 0x1000 0x00 0xfd10e000 0x00 0x1000 0x00 0xfd10f000 0x00 0x1000 0x00 0xfd12c000 0x00 0x1000 0x00 0xfd12d000 0x00 0x1000 0x00 0xfd12e000 0x00 0x1000 0x00 0xfd12f000 0x00 0x1000>;
	};

	debug@fd104000 {
		compatible = "rockchip,debug";
		reg = <0x00 0xfd104000 0x00 0x1000 0x00 0xfd105000 0x00 0x1000 0x00 0xfd106000 0x00 0x1000 0x00 0xfd107000 0x00 0x1000 0x00 0xfd124000 0x00 0x1000 0x00 0xfd125000 0x00 0x1000 0x00 0xfd126000 0x00 0x1000 0x00 0xfd127000 0x00 0x1000>;
	};

	fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <0x02>;
		rockchip,wake-irq = <0x00>;
		rockchip,irq-mode-enable = <0x01>;
		rockchip,baudrate = <0x16e360>;
		interrupts = <0x00 0x1a7 0x08>;
		pinctrl-names = "default";
		pinctrl-0 = <0x13b>;
		status = "disabled";
	};

	ramoops@110000 {
		compatible = "ramoops";
		reg = <0x00 0x110000 0x00 0xf0000>;
		record-size = <0x20000>;
		console-size = <0x80000>;
		ftrace-size = <0x00>;
		pmsg-size = <0x50000>;
	};

	reserved-memory {
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;

		cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x00 0x800000>;
			linux,cma-default;
		};

		drm-logo@00000000 {
			compatible = "rockchip,drm-logo";
			reg = <0x00 0x00 0x00 0x00>;
			phandle = <0x33>;
		};

		drm-cubic-lut@00000000 {
			compatible = "rockchip,drm-cubic-lut";
			reg = <0x00 0x00 0x00 0x00>;
		};
	};

	adc-keys {
		compatible = "adc-keys";
		io-channels = <0x175 0x01>;
		io-channel-names = "buttons";
		keyup-threshold-microvolt = <0x1b7740>;
		poll-interval = <0x64>;

		vol-up-key {
			label = "volume up";
			linux,code = <0x73>;
			press-threshold-microvolt = <0x4268>;
		};

		vol-down-key {
			label = "volume down";
			linux,code = <0x72>;
			press-threshold-microvolt = <0x65ce8>;
		};

		menu-key {
			label = "menu";
			linux,code = <0x8b>;
			press-threshold-microvolt = <0xd9490>;
		};

		back-key {
			label = "back";
			linux,code = <0x9e>;
			press-threshold-microvolt = <0x12d838>;
		};
	};

	backlight {
		compatible = "pwm-backlight";
		brightness-levels = <0x00 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>;
		default-brightness-level = <0xc8>;
		pwms = <0x176 0x00 0x61a8 0x00>;
		status = "okay";
		phandle = <0xd2>;
	};

	dp0-sound {
		status = "okay";
		compatible = "rockchip,hdmi";
		rockchip,card-name = "rockchip,dp0";
		rockchip,mclk-fs = <0x200>;
		rockchip,cpu = <0x177>;
		rockchip,codec = <0x178 0x01>;
		rockchip,jack-det;
	};

	hdmi0-sound {
		status = "okay";
		compatible = "rockchip,hdmi";
		rockchip,mclk-fs = <0x80>;
		rockchip,card-name = "rockchip-hdmi0";
		rockchip,cpu = <0x179>;
		rockchip,codec = <0x17a>;
		rockchip,jack-det;
	};

	es8316-sound {
		status = "okay";
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,mclk-fs = <0x100>;
		simple-audio-card,name = "rockchip,es8316-codec";

		simple-audio-card,dai-link@0 {
			format = "i2s";

			cpu {
				sound-dai = <0x17b>;
			};

			codec {
				sound-dai = <0x17c>;
			};
		};
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl- = <0x17d>;
		status = "okay";

		led-red {
			label = "led1-r";
			gpios = <0x12f 0x18 0x00>;
			default-state = "off";
		};

		led-green {
			label = "led2-g";
			gpios = <0x12f 0x14 0x00>;
			default-state = "off";
		};
	};

	test-power {
		status = "okay";
	};

	rk-headset {
		status = "okay";
		compatible = "rockchip_headset";
		io-channels = <0x175 0x03>;
	};

	sdio-pwrseq {
		compatible = "mmc-pwrseq-simple";
		clocks = <0x17e>;
		clock-names = "ext_clock";
		pinctrl-names = "default";
		pinctrl-0 = <0x17f>;
		post-power-on-delay-ms = <0xc8>;
		reset-gpios = <0x12f 0x17 0x01>;
		phandle = <0xf8>;
	};

	vcc12v-dcin {
		compatible = "regulator-fixed";
		regulator-name = "vcc12v_dcin";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0xb71b00>;
		regulator-max-microvolt = <0xb71b00>;
		phandle = <0x180>;
	};

	vcc5v0-sys {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		vin-supply = <0x180>;
		phandle = <0x65>;
	};

	vcc5v0-usbdcin {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_usbdcin";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		vin-supply = <0x180>;
		phandle = <0x181>;
	};

	vcc5v0-usb {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_usb";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		vin-supply = <0x181>;
	};

	combophy-avdd0v85 {
		compatible = "regulator-fixed";
		regulator-name = "combophy_avdd0v85";
		regulator-boot-on;
		regulator-always-on;
		regulator-min-microvolt = <0xcf850>;
		regulator-max-microvolt = <0xcf850>;
		vin-supply = <0x182>;
	};

	combophy-avdd1v8 {
		compatible = "regulator-fixed";
		regulator-name = "combophy_avdd1v8";
		regulator-boot-on;
		regulator-always-on;
		regulator-min-microvolt = <0x1b7740>;
		regulator-max-microvolt = <0x1b7740>;
		vin-supply = <0x183>;
	};

	pwm-fan {
		compatible = "pwm-fan";
		#cooling-cells = <0x02>;
		pwms = <0x184 0x00 0xf4240 0x00>;
	};

	vcc3v3-lcd0-n {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3_lcd0_n";
		regulator-boot-on;
		regulator-always-on;
		enable-active-high;
		gpio = <0xeb 0x12 0x00>;
		vin-supply = <0x185>;
	};

	vcc5v0-host {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_host";
		regulator-boot-on;
		regulator-always-on;
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		enable-active-high;
		gpio = <0xeb 0x10 0x00>;
		vin-supply = <0x65>;
		pinctrl-names = "default";
		pinctrl-0 = <0x186>;
		phandle = <0x62>;
	};

	vcc5v0-otg {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_otg";
		regulator-boot-on;
		regulator-always-on;
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		enable-active-high;
		gpio = <0xeb 0x11 0x00>;
		vin-supply = <0x65>;
		pinctrl-names = "default";
		pinctrl-0 = <0x187>;
		phandle = <0x61>;
	};

	vcc-1v1-nldo-s3 {
		compatible = "regulator-fixed";
		regulator-name = "vcc_1v1_nldo_s3";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x10c8e0>;
		regulator-max-microvolt = <0x10c8e0>;
		vin-supply = <0x65>;
		phandle = <0x136>;
	};

	vcc-mipi-dphy0 {
		compatible = "regulator-fixed";
		regulator-name = "vcc_mipidphy0";
		regulator-min-microvolt = <0x124f80>;
		regulator-max-microvolt = <0x124f80>;
		gpios = <0x188 0x06 0x00>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <0x189>;
		pinctrl-names = "default";
		pinctrl-0 = <0x18a>;
		phandle = <0x159>;

		regulator-state-mem {
			regulator-off-in-suspend;
		};
	};

	vcc-3v3-sd-s0 {
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3_sd_s0";
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		enable-active-low;
		vin-supply = <0x189>;
		phandle = <0xf4>;
	};

	wireless-bluetooth {
		compatible = "bluetooth-platdata";
		clocks = <0x17e>;
		clock-names = "ext_clock";
		uart_rts_gpios = <0xeb 0x1a 0x01>;
		pinctrl-names = "default\0rts_gpio";
		pinctrl-0 = <0x18b 0x18c 0x18d 0x18e>;
		pinctrl-1 = <0x18f>;
		BT,reset_gpio = <0x12f 0x1b 0x00>;
		BT,wake_gpio = <0x12f 0x16 0x00>;
		BT,wake_host_irq = <0x12f 0x15 0x00>;
		status = "okay";
	};

	wireless-wlan {
		compatible = "wlan-platdata";
		wifi_chip_type = "ap6256";
		pinctrl-names = "default";
		pinctrl-0 = <0x190>;
		WIFI,host_wake_irq = <0x12f 0x00 0x00>;
		status = "okay";
	};
};